3D Conductive Pillar Memory With Variable Resistance Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration with reduced process complexity while maintaining excellent memory cell characteristics and operational performance, particularly due to material reactivity issues and integration difficulties in memory circuits.
Innovation Solution
The electronic device incorporates conductive pillars and variable resistance layers with distinct material layers, including metal nitride or noble metals, arranged in a specific structure over a substrate, with insulation and selection device layers to control resistance states, allowing for high integration and stable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional memory device structures are used, then manufacturing process is simpler, but integration degree is lower
Solution Approach 1:
The patent transitions from planar 2D memory cell layouts to a 3D vertical architecture where conductive pillars extend perpendicular to the substrate. Multiple variable resistance layers are stacked vertically between conductive pillars, enabling three-dimensional integration. This dimensional change increases integration density without proportionally increasing process complexity, as the vertical stacking follows systematic fabrication sequences.
Solution Approach 2:
The patent implements nested structures where variable resistance layers are positioned between conductive pillars, with conductive patterns embedded within insulating layers. The conductive pillars are surrounded by variable resistance layers, which are in turn surrounded by conductive patterns and insulating layers, creating a nested configuration that maximizes space utilization and integration degree.
2Reliability
If material layers with high reactivity are used, then electrical conductivity is improved, but manufacturing reliability deteriorates
Solution Approach 1:
The patent introduces insulating layers as intermediary barriers between conductive pillars and conductive patterns. These insulating layers prevent direct contact between reactive metal materials, eliminating harmful chemical reactions while maintaining electrical conductivity through controlled interfaces. The insulating layers act as mediators that enable the use of high-reactivity materials without compromising manufacturing reliability.
Solution Approach 2:
The patent employs composite material structures combining metal nitride or noble metals for conductive pillars with insulating materials such as oxides or nitrides. This composite approach leverages the high conductivity of metals while the insulating components prevent unwanted reactions. The composite structure achieves both excellent electrical performance and manufacturing reliability by combining materials with complementary properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances integration degree, reduces process complexity, and maintains excellent memory cell characteristics, achieving high operation rates and stable performance with reduced fabrication costs.
Implementation Method 1
a variable resistance layer disposed between the conductive pillar and the conductive pattern adjacent to the conductive pillar
Implementation Method 2
conductive pillars stretched in a direction perpendicular to a substrate... conductive patterns disposed between the conductive pillars
Data Source
AI summary
An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes a plurality of conductive pillars stretching in a direction perpendicular to a substrate, the plurality of conductive pillars arranged in a first direction and a second direction intersecting the first direction, conductive patterns disposed between the conductive pillars, variable resistance layers each of which is disposed between a corresponding one of the conductive pillars and a corresponding one of the conductive patterns, said each of the variable resistance layers contacting the corresponding conductive pattern and the corresponding conductive pillar, first lines disposed between the conductive pillars in the second direction and stretch in the first direction, the first lines contacting the conductive patterns under the conductive patterns, and second lines disposed between the conductive pillars in the first direction and stretch in the second direction, the second lines contacting the conductive patterns over the conductive patterns.