3D Copper PCB Structures for Low-Resistance Power Delivery
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Solution Overview
Problem
Conventional PCB architectures face challenges in delivering power to low voltage, high current processors due to limited copper cross-sectional area, leading to increased DC resistance and thermal issues, which are exacerbated by the need for thicker copper planes that restrict design flexibility and increase material and fabrication costs.
Innovation Solution
Incorporation of 3D conductive material trenches and buried vias in PCBs, formed through laser drilling and electroless/electrolytic plating, to enhance copper cross-sectional area and reduce DC resistance, while maintaining mechanical strength and thermal conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thicker copper planes are used to increase current carrying capacity, then current density limits are satisfied, but design flexibility is restricted and material costs increase
Solution Approach 1:
The patent transitions from two-dimensional copper traces on PCB layers to three-dimensional copper structures by filling vias and trenches with copper. This vertical dimensionality allows current to flow through multiple layers simultaneously, dramatically increasing current carrying capacity without requiring thicker individual copper planes, thereby preserving design flexibility.
Solution Approach 2:
The patent embeds copper-filled vias and trenches within the multi-layer PCB structure. These 3D copper features are nested between standard PCB layers, utilizing the vertical space efficiently. The copper fills the void spaces within the PCB stackup, adding current carrying capacity without increasing the overall PCB thickness or requiring thicker copper planes.
2Reliability
If thicker copper planes are used to reduce DC resistance, then power delivery improves, but material usage and fabrication costs increase
Solution Approach 1:
By creating vertical copper pathways through via filling and trench filling, the patent reduces the horizontal current path length and distributes current across multiple layers. This 3D current distribution reduces DC resistance without requiring proportionally more copper material, as the same amount of copper is utilized more efficiently in three dimensions.
Solution Approach 2:
The patent changes the geometric parameters of copper features from thin 2D traces to thick 3D structures by filling vias and trenches. This parameter change increases the effective copper cross-sectional area for current flow, reducing DC resistance. The process uses standard plating thicknesses applied to 3D geometries rather than requiring uniformly thicker copper planes throughout.
3Reliability
If standard mechanical drilled vias are used for z-axis connections, then connection reliability is achieved, but copper cross-sectional area is limited by thin plating layers
Solution Approach 1:
The patent applies electroless copper plating to the walls of mechanical drilled vias before filling. This preliminary copper coating creates a conductive base that allows subsequent electrolytic copper filling to proceed uniformly. The pre-plated copper ensures reliable electrical connection along the via walls while the subsequent fill maximizes the copper cross-sectional area, combining connection reliability with high current capacity.
4Reliability
If laser drilled vias are used to increase copper density, then current carrying capacity improves, but the funnel shape limits uniform copper distribution
Solution Approach 1:
The patent uses electroless copper plating as a preliminary step before electrolytic filling. The electroless process uniformly deposits copper on the funnel-shaped via walls regardless of the laser drill geometry, creating a consistent conductive base layer. This preliminary action compensates for the non-uniform geometry, ensuring uniform copper distribution and reliable electrical properties throughout the via fill.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides improved current carrying capacity, reduced DC resistance, and increased thermal reliability with enhanced mechanical strength, allowing for more efficient power delivery to high current processors without increasing PCB thickness or material usage.
Implementation Method 1
Trenches may be formed in dielectric layers in build-up layers of the PCB by overlapping multiple laser drilled vias
Implementation Method 2
The trenches formed may be filled with solid conductive material using a combination of electroless plating and electrolytic plating of conductive material
Implementation Method 3
The trenches formed may be filled with solid conductive material using a combination of electroless plating and electrolytic plating of conductive material
Data Source
AI summary
Structures that implement three-dimensional (3D) conductive material (e.g., copper) in printed circuit boards (PCBs) are disclosed. 3D (three-dimensional) conductive material may include trenches and/or buried vias that are filled with conductive material in the PCBs. Trenches may be formed in build-up layers of a PCB by overlapping multiple laser drilled vias. The trenches may be filled with conductive material using electroplating process(es). Buried vias may be formed through the core layers of the PCB by mechanical drilling. The buried via may be filled with solid conductive material using a combination of electroless plating and electrolytic plating of conductive material. Various PCB structures are disclosed that implement combinations of these trenches and/or these buried vias filled with conductive material.