3D IC Copper-to-Copper Wafer Bonding
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Solution Overview
Problem
The increasing cost of mask sets for semiconductor manufacturing and the limitations of Through-Silicon-Via (TSV) technology in achieving high vertical connectivity in 3D Integrated Circuits (ICs) pose challenges for device scaling and performance enhancement.
Innovation Solution
The development of 3D IC devices using copper interconnecting layers and copper-to-copper bonding between wafers, with vias of less than 1 micron radius, and the integration of antifuse-based programmable logic to reduce development costs and enhance connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Through-Silicon-Via (TSV) technology is used for 3D IC interconnection, then vertical connectivity is achieved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from planar 2D interconnection to three-dimensional 3D interconnection by stacking multiple semiconductor wafers vertically. This dimensional change enables vertical connectivity through copper interconnecting layers and copper-to-copper bonding, achieving higher integration density while managing the complexity through systematic 3D architecture design.
2Manufacturing precision
If mask set cost increases for new process technology, then manufacturing precision improves, but manufacturing cost increases
Solution Approach 1:
The patent employs advanced copper interconnection technology with via radii less than 1 micron, representing a parameter change in interconnection dimensions. This enables higher precision manufacturing while the copper-to-copper bonding and antifuse-based programmable logic provide cost-effective solutions for achieving the required manufacturing precision without proportionally increasing mask set costs.
3Speed
If wire length is reduced in 3D stacking, then performance improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent achieves short wire lengths by transitioning from lateral 2D routing to vertical 3D routing through stacked wafers. The copper interconnecting layers and vias with radius less than 1 micron enable direct vertical connections between functional blocks on different wafers, significantly reducing signal path length while managing precision requirements through advanced fabrication processes.
4Adaptability or versatility
If antifuse-based programmable logic is integrated, then adaptability improves, but device complexity increases
Solution Approach 1:
The patent integrates antifuse-based programmable logic into the 3D IC structure, enabling the device to perform multiple functions and be reconfigured for different applications. The antifuse structures provide programmable interconnectivity between copper interconnecting layers, allowing the same hardware platform to adapt to various computational tasks while managing complexity through standardized programmable logic blocks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides an order of magnitude improvement in vertical connectivity and reduces development costs, enabling more efficient and high-density 3D IC designs with improved performance and power management.
Implementation Method 1
first copper interconnecting layers, wherein said first copper interconnecting layers at least interconnect said plurality of first transistors
Implementation Method 2
wherein said second wafer is bonded face-to-face on top of said first wafer, wherein said bonded comprises copper to copper bonding
Data Source
AI summary
A 3D integrated circuit, the circuit including: a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; and a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; where the second wafer is bonded face-to-face on top of the first wafer, where the bonded includes copper to copper bonding; and where the second crystalline substrate has been thinned to a thickness of less than 5 micro-meters.