Transistor TRIZ Cases

Parallel carbon nanowall thin films form a channel layer to pass larger electric currents, overcoming single-nanowall capacity limits.

A semiconductor device uses variable fin pitch and cavity work function metal to define distinct threshold voltages.

An oxide semiconductor thin film transistor aligns the gate electrode with the channel region to reduce parasitic capacitance and enhance charge mobility.

A TiN barrier layer inside the contact structure stops NiPt diffusion into dielectrics, maintaining low on-resistance during device scaling.

A semiconductor device structure using a shared silicon layer as a common electrode for stacked capacitive elements.

Annealing oxide semiconductor bottom electrodes increases carrier density through hydrogen diffusion from insulation layers.

A vertical fin field effect transistor uses a self-aligned gate structure with segmented fins to control feature placement.

An inorganic insulating film positioned to avoid overlapping with thin-film transistor channel regions protects semiconductor layers from hydrogen entry.

A conductive reaction suppression layer connects ohmic and Schottky electrodes in a silicon carbide metal plate schottky diode.

Vertical trench contacts and fill metal create a 3D MIM capacitor that reduces chip area consumption while maintaining CMOS compatibility.

Merging capacitor dielectric and gate insulation layers reduces photolithography mask steps, lowering manufacturing complexity and cost.

Asymmetric dielectric layer thicknesses enable electron tunneling for erase operations while preventing breakdown between the erase gate and source region.

A self-triggered semiconductor device uses complementary doped fins to form bipolar junction transistors that bypass electrostatic discharge currents.

A semiconductor device uses a super-connect interconnection structure with thick insulating layers to reduce parasitic capacitance.

Controlled oxidation forms a graded oxide barrier on copper alloy wiring to suppress electromigration without adding complex external films.

A replacement metal gate process forms self-aligned shared contacts between adjacent fins in vertical transport field-effect transistors.

Thick gate native transistors isolate standard components to reduce gate leakage currents in oscillator circuits.

Embedded PN diodes add block voltage to lateral NPN BJT snapback, reducing trigger-to-holding gap and preventing IC damage.

A semiconductor device forms two insulation layers with distinct patterns using a single mask process and photosensitive material.

Thicker gate isolation films in SOI MOS power switches reduce sub-threshold leak current while maintaining low ON-state resistance.

A nitride semiconductor pn diode structure prevents electrical failure in high-power devices.

A method deposits an amorphous oxide semiconductor film under controlled oxygen partial pressure to enable subsequent crystallization.

Resin passivation layer directly covers source and drain electrodes on a TFT array substrate to simplify the manufacturing sequence.

A dielectric layer covers an initial fin with a thinner top region to define the final channel width during etching.

Alternating N-type and P-type photodiodes create potential barriers that minimize electrical influences between adjacent pixels in image sensors.

A method uses a dummy gate and external spacers to self-align internal spacers via selective etching.

Insulating barrier layers isolate the sub-fin region in nanosheet transistors, eliminating leakage caused by random dopant fluctuations.

A recessed gate structure reduces electric field magnitudes in the drift region of a trench FET to enable bidirectional blocking.

Segmenting continuous floating gates into discrete regions via nanoparticle masks reduces programming voltage and power consumption.

A semiconductor device uses p-type ring-shaped regions and a semi-insulating layer to stabilize depletion layer spreading.

Integrating transistors and capacitors into the substrate reduces assembly complexity while maintaining high performance through vertical proximity.

Gate electrodes use impurity concentration to control depletion and secure electrical effective thicknesses for insulating films.

A metal-containing liner shields sidewall spacers from etch damage, reducing parasitic capacitance in nanosheet transistors.

Stacked capacitance electrodes separated by a dielectric layer increase overlap area while allowing the shield layer to fully cover relay wiring.

Polysilicon burial of non-operating gates reduces the work function and Gate Induced Drain Leakage, resolving refresh characteristic deterioration.

Germanium-rich protection layers shield epitaxial source/drain regions from etching damage, maintaining device reliability as feature sizes shrink.

A semiconductor gate stack uses a shared capping layer to protect high-k dielectrics during sequential deposition of distinct work function materials.

Series-connected crown-shaped capacitance blocks share an upper electrode to minimize planar area.

Shared well STSCRs reduce layout area and pin-to-pin current paths, protecting gate oxides from parasitic capacitance degradation.

Segmented charge balance regions distribute electric field stress across the termination area of a superjunction semiconductor device.

Double-gated transistors in a CMOS image sensor adjust threshold voltage dynamically to reduce leakage current while maintaining full dynamic range.

Time multiplexed ESD trigger signals activate clamps to divert charge from system level events with faster rise times and higher peak currents.

Recessed source-drain regions filled with epitaxial layers reduce contact resistance while minimizing junction leakage current.

Different transistor sizes resolve reliability and noise trade-offs by optimizing electrical characteristics within photoelectric conversion devices.

Sidewall spacer and filler masking creates solid pillars with doubled pitch, resolving limits in photolithography resolution and process complexity.

A segmented oxide semiconductor film with a protective cap layer resolves the contradiction between miniaturization and surface flatness, enabling high yield.

A high mobility oxide liner lowers Schottky barrier height to reduce contact resistance in thin film transistors.

Dual mask ion implantation reduces source drain resistance in NMOS transistors while preventing channel diffusion that causes threshold voltage variability.