Capacitance Element Stacked Electrodes Shielding Area
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Solution Overview
Problem
In active driven type liquid crystal devices, the relay wiring connected to the pixel electrode is not completely covered by the shield layer, limiting the effective use of capacitance wiring area and resulting in reduced capacitance.
Innovation Solution
The configuration includes a transistor with a gate electrode, source and drain regions, a pixel electrode connected to a scanning line, a data line, and a capacitance element with a first and second capacitance electrode separated by a dielectric layer, where the first capacitance electrode is covered by the dielectric layer and the second capacitance electrode is positioned between the transistor, scanning line, and data line layers, allowing increased overlap area and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the relay wiring is arranged in a lower layer than the shield layer, then the shield layer can provide electromagnetic shielding, but the relay wiring cannot be completely covered by the shield layer, reducing the effective capacitance wiring area
Solution Approach 1:
The patent changes the spatial arrangement from a planar configuration to a three-dimensional stacked configuration. The first capacitance electrode is placed in the lower layer, the dielectric layer is formed above it, and the second capacitance electrode is placed in the upper layer, allowing the shield layer to completely cover the relay wiring while maintaining effective capacitance wiring area through vertical stacking.
2Device complexity
If the dielectric layer and second capacitance electrode are merely arranged on the first capacitance electrode, then the structure is simple, but the overlap area between capacitance electrodes is limited, reducing capacitance
Solution Approach 1:
The patent implements a nested structure where the first capacitance electrode is embedded in the lower layer, the dielectric layer envelops it partially, and the second capacitance electrode is positioned in the upper layer to overlap with the first electrode. This nested arrangement maximizes the overlap area between capacitance electrodes, thereby increasing capacitance while maintaining structural compactness.
3Quantity of substance
If the first capacitance electrode is arranged to be covered with the dielectric layer and second capacitance electrode, then the overlap area increases and capacitance increases, but the manufacturing process becomes more complex
Solution Approach 1:
The patent segments the capacitance element into distinct functional layers: the first capacitance electrode layer, the dielectric layer, and the second capacitance electrode layer. Each layer is formed through separate manufacturing steps, allowing for precise control of each component's properties and simplifying the overall manufacturing process despite the increased structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the capacitance of the capacitance element, effectively uses the capacitance electrode area, and prevents reduction in aperture ratio, thereby improving display quality in electronic apparatus.
Implementation Method 1
a capacitance element which has a first capacitance electrode electrically connected to a capacitance line, a second capacitance electrode provided to oppose the first capacitance electrode, and a dielectric layer interposed between the first capacitance electrode and the second capacitance electrode
Data Source
AI summary
Disclosed is a pixel electrode which is electrically connected to a scanning line electrically connected to a gate electrode, a data line electrically connected to a data line side source and drain region, and a pixel electrode side source and drain region; and a capacitance element which has a first capacitance electrode which is electrically connected to a capacitance line, a second capacitance electrode which is provided to oppose the first capacitance electrode, and a dielectric layer which is interposed between the first capacitance electrode and the second capacitance electrode, where the first capacitance electrode is arranged to be covered with the dielectric layer and the second capacitance electrode between a layer where the transistor, the scanning line, and the data line are provided and a layer where the pixel electrode is provided.