Flash Cell Structure with Asymmetric Dielectric Layers for Erase Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional flash cell structures face a tradeoff in the thickness of the inter poly oxide layer, where a thick layer between the erase gate and floating gate can lead to failed erase operations, while a thin layer between the erase gate and source region can result in breakdown, necessitating a new design to optimize this thickness.
Innovation Solution
A flash cell structure is designed with the total thickness of the first and third dielectric layers between the erase gate and floating gate being less than the total thickness of the second and third dielectric layers between the erase gate and the first doped region, allowing easier tunneling of electrons during erase operations without causing breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the thickness of the inter poly oxide between erase gate and source region is decreased, then the cell size is reduced, but the breakdown risk increases
Solution Approach 1:
The patent implements local quality by positioning thicker dielectric layers (second dielectric layer: 150-300 nm) specifically at locations where breakdown risk is highest, namely between the erase gate and source/drain regions. This localized thickness enhancement provides targeted protection against dielectric breakdown while allowing thinner regions elsewhere to minimize overall cell size.
Solution Approach 2:
The patent segments the dielectric structure into multiple layers with the second dielectric layer specifically positioned between the erase gate and source/drain regions. This segmentation allows the design to maintain thin overall dimensions for small cell size while providing locally enhanced thickness where electrical breakdown protection is critical.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables successful erase operations by ensuring that electrons can tunnel through the dielectric layers between the erase gate and floating gate without breaking the layers between the erase gate and the doped region, thereby improving the reliability of the flash cell structure.
Implementation Method 1
the total thickness of the first dielectric layer and the third dielectric layer between the erase gate and the floating gate being less than the total thickness of the second dielectric layer and the third dielectric layer between the erase gate and the first doped region
Data Source
AI summary
The present invention provides a flash cell structure and a method of fabricating the same. The flash cell structure includes a semiconductor substrate, a stacked gate structure disposed on the semiconductor substrate, a first doped region disposed in the semiconductor substrate at a side of the stacked gate structure, a first dielectric layer, a second dielectric layer, and an erase gate. The stacked gate structure includes a floating gate insulated from the semiconductor substrate and a control gate disposed on the floating gate and insulated from the floating gate. The first dielectric layer is disposed on a sidewall of the floating gate. The second dielectric layer is disposed on the first doped region. A thickness of the first dielectric layer is less than a thickness of the second dielectric layer.