Semiconductor Gate Stack with Shared Capping Layer for Threshold Voltage Control
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down integrated circuit (IC) technology, particularly in forming gate stacks for advanced transistors, where traditional methods struggle to maintain dielectric properties and prevent material diffusion, leading to issues with threshold voltage control and transistor performance.
Innovation Solution
The use of a sequential deposition process for high-k layers, capping layers, work function layers, and gate fill materials, including TaN and TiAl, with specific etching techniques to pattern work function layers, ensures the protection of high-k layers and allows for different work function tuning in transistors, enabling multi-threshold voltage designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional deposition and patterning methods are used for gate stack formation, then the fabrication process is simpler, but dielectric properties deteriorate and material diffusion occurs leading to poor threshold voltage control
Solution Approach 1:
The gate stack fabrication is divided into multiple sequential deposition steps, with each layer (high-k dielectric, capping layer, work function layer) deposited and patterned separately. This segmentation allows precise control of each interface and prevents material diffusion, directly improving threshold voltage control despite increasing process complexity
Solution Approach 2:
A capping layer is deposited over the high-k dielectric layer before subsequent processing steps. This preliminary action protects the high-k dielectric from contamination and prevents material diffusion during later deposition and etching steps, ensuring maintained dielectric properties and improved reliability
2Adaptability or versatility
If a single work function layer is used, then the fabrication process is simpler, but threshold voltage tuning flexibility is limited
Solution Approach 1:
Different work function layers with distinct material properties are used in different regions of the gate structure. This allows independent tuning of threshold voltages for different transistor types (n-type and p-type) within the same device, providing adaptability for multi-threshold voltage designs while managing complexity through functional specialization
Solution Approach 2:
Multiple work function layers with different materials (e.g., titanium nitride, tantalum nitride) are stacked together to create a composite gate structure. This composite approach enables precise control over work function and threshold voltage by selecting and combining materials with appropriate electronic properties, enhancing tuning flexibility
3Productivity
If geometry size is scaled down to increase functional density, then production efficiency and cost are improved, but maintaining dielectric properties and preventing material diffusion become more difficult
Solution Approach 1:
The capping layer is deposited over the high-k dielectric before any subsequent processing. This preliminary protective action prevents material diffusion and contamination that would be particularly problematic at scaled dimensions, maintaining dielectric properties even as geometry shrinks to improve productivity
Solution Approach 2:
The gate stack is segmented into multiple thin layers deposited sequentially. At scaled dimensions, this segmentation allows each interface to be precisely controlled and minimizes inter-diffusion, maintaining reliable dielectric properties while enabling the continued scaling needed for production efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the dielectric properties of gate stacks, prevents material diffusion, and allows for precise threshold voltage control, enabling the fabrication of transistors with varied performance characteristics, facilitating more complex and efficient IC designs.
Implementation Method 1
a first gate structure disposed over the first semiconductor fin, the second gate structure disposed over the second semiconductor fin
Implementation Method 2
sequential deposition process for high-k layers, capping layers, work function layers, and gate fill materials
Implementation Method 3
patterned by removing a portion of the work function layer with a halogen based etchant
Data Source
AI summary
A semiconductor device may include a substrate, a first transistor disposed on the substrate, and a second transistor disposed on the substrate. The first gate structure of the first transistor may include a first high-k layer, a first capping layer and a first work function layer sequentially disposed on the substrate. A material of the first work function layer includes Ta. The second transistor includes a second gate structure. The second gate structure includes a second high-k layer, a second capping layer and a second work function layer sequentially disposed on the substrate. The first capping layer and the second capping layer are formed of the same layer, and a material of the second work function layer is different from the material of the first work function layer.