Vertical FinFET Self-Aligned Gate Segmentation
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Solution Overview
Problem
The challenge lies in forming smaller device components for Field Effect Transistors (FETs) while maintaining the positive aspects of traditional FET structures, as scaling issues arise with decreasing device dimensions, making it difficult to align lithography masks with existing fins on a substrate, leading to misplacement of features and incorrect placement of subsequent components.
Innovation Solution
A method is developed for forming vertical fin FETs with a self-aligned gate structure, involving the formation of vertical fins, gate dielectric layers, a fin-cut mask layer, and fin trenches to create separated fin segments, along with a doped layer and dielectric fill, allowing for precise control of feature placement and separation distances between fin segments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are decreased to increase device density, then device density is improved, but manufacturing precision deteriorates due to alignment difficulties
Solution Approach 1:
The gate structure is divided into multiple discrete gate segments separated by fin trenches, allowing each segment to be independently formed and positioned. This segmentation enables precise control of gate features at reduced dimensions while maintaining manufacturing precision through self-aligned formation processes.
Solution Approach 2:
The patent transitions from planar gate structures to three-dimensional vertical fin structures with gates wrapping around the fins. By utilizing the vertical dimension and creating fin trenches that extend into the substrate, the process achieves precise feature placement in multiple dimensions, overcoming the limitations of two-dimensional lithographic alignment.
2Ease of manufacture
If traditional lithography alignment methods are used, then process simplicity is maintained, but feature placement accuracy deteriorates at smaller dimensions
Solution Approach 1:
The fin structures are formed first as self-aligned templates before the gate segments are deposited. The fin trenches are then formed to precisely define gate segment positions. This preliminary formation of structural templates eliminates the need for complex lithographic alignment steps, maintaining process simplicity while achieving high feature placement accuracy through self-alignment.
Solution Approach 2:
The fin structures and fin trenches serve as self-aligned references that automatically define the positions of gate segments and other features. The process uses the device's own structural elements as alignment references, eliminating the need for external lithographic alignment and achieving precise feature placement without increasing process complexity.
3Quantity of substance
If fin segments are placed closer together to increase density, then device density is improved, but placement variation increases
Solution Approach 1:
The gate is segmented into discrete sections separated by fin trenches, with each segment's position defined by the underlying fin structure and fin trench geometry. This segmentation allows tight spacing between segments while maintaining precise placement control through self-aligned formation, reducing placement variation even at high device densities.
Solution Approach 2:
The patent uses vertical fin structures and fin trenches extending into the substrate to define gate segment positions in three dimensions. This three-dimensional self-aligned approach provides precise placement control that is insensitive to lateral lithographic variations, enabling tight segment spacing with minimal placement variation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurate placement and separation of device features, overcoming scaling issues and misalignment problems, thereby improving device density and reducing variations in feature placement, enhancing the performance of FETs.
Implementation Method 1
annealing the fin liner to form a doped layer on at least a portion of the vertical fin segments exposed in the fin trench(es)
Implementation Method 2
annealing the fin liner to form a doped layer on at least a portion of the vertical fin segments
Data Source
AI summary
A method of forming a vertical fin field effect transistor with a self-aligned gate structure, comprising forming a plurality of vertical fins on a substrate, forming gate dielectric layers on opposite sidewalls of each vertical fin, forming a gate fill layer between the vertical fins, forming a fin-cut mask layer on the gate fill layer, forming one or more fin-cut mask trench(es) in the fin-cut mask layer, and removing portions of the gate fill layer and vertical fins not covered by the fin-cut mask layer to form one or more fin trench(es), and two or more vertical fin segments from each of the plurality of vertical fins, having a separation distance, D1, between two vertical fin segments.