MOS Transistor Recessed Source-Drain Epitaxial Growth
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Solution Overview
Problem
The formation of crystalline defects during ion implantation in semiconductor substrates complicates the growth of uniform epitaxial layers in MOS transistors, leading to increased junction leakage current and contact resistance, especially when using elevated source/drain structures.
Innovation Solution
The implementation of recessed regions in the semiconductor substrate, filled with impurity-doped epitaxial layers and covered with metal silicide, reduces crystalline defects by using chemical dry etching and selective epitaxial growth techniques, maintaining low contact resistance and minimizing junction leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implantation is used to form source/drain regions, then contact resistance is reduced, but crystalline defects are generated that complicate epitaxial layer growth
Solution Approach 1:
The patent performs preliminary annealing treatment before epitaxial layer formation to repair crystalline defects caused by ion implantation. This preliminary action restores the crystal structure, enabling subsequent uniform epitaxial growth while maintaining the low contact resistance achieved through ion implantation.
Solution Approach 2:
The patent changes the physical and chemical parameters of the semiconductor substrate through controlled annealing processes. By adjusting temperature, time, and atmosphere parameters, the crystalline defects are eliminated without compromising the electrical properties achieved by ion implantation.
2Manufacturing precision
If annealing time or temperature is increased to reduce crystalline defects, then epitaxial layer quality improves, but impurity diffusion in extension regions increases causing short channel effect
Solution Approach 1:
The patent applies local quality by performing selective annealing in different regions. The extension regions receive controlled annealing treatment to reduce defects without excessive impurity diffusion, while source/drain regions maintain their low resistance properties. This spatially differentiated treatment resolves the contradiction between defect reduction and impurity diffusion control.
3Productivity
If shallow junction depth is used, then device integration is improved, but junction leakage current increases
Solution Approach 1:
The patent performs preliminary defect repair through annealing before forming the epitaxial layer on shallow junctions. This preliminary action eliminates crystalline defects that would otherwise cause leakage, enabling shallow junction depths to be used without increasing leakage current, thus maintaining both high integration and low leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of MOS transistors with reduced crystalline defects, enabling uniform epitaxial growth and lower contact resistance without the need for increased annealing time or temperature, thus improving the performance of highly integrated MOS transistors.
Implementation Method 1
an epitaxial layer is grown on the impurity doped region that fills the recess
Implementation Method 2
a metal silicide layer is formed on the epitaxial layer to lower the contact resistance
Data Source
AI summary
Metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions and methods of fabricating the same are provided. The MOS transistors may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.