TFT Array Substrate with Merged Insulation Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The manufacturing of flat panel display devices, such as organic light emitting display devices, is complex and costly due to the need for multiple mask processes in photolithography, which increases the time and expense of producing minute patterns of thin-film transistors, capacitors, and wires on substrates.
Innovation Solution
A thin-film transistor array substrate design with a specific layer structure and manufacturing method that includes a thin-film transistor with active and insulation layers, a pixel electrode with a semi-transmission metal layer, and a capacitor with separate dielectric and protection layers, allowing for simpler and more efficient manufacturing processes by using fewer mask steps and optimizing insulation layer thickness and material selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple mask processes are used in photolithography to form minute patterns of TFT, capacitor, and wire, then the manufacturing precision is improved, but the device complexity and manufacturing cost are increased
Solution Approach 1:
The patent combines the formation of the capacitor dielectric layer and the TFT gate insulation layer into a single insulation layer structure. This merging of functions reduces the number of separate photolithography mask processes required, thereby simplifying the manufacturing process while maintaining the precision needed for forming minute patterns of TFTs, capacitors, and wires on the substrate
2Manufacturing precision
If multiple mask processes are used in photolithography, then the manufacturing precision is improved, but the manufacturing time is increased
Solution Approach 1:
By merging the capacitor dielectric and TFT gate insulation into a single layer, the patent reduces the sequential steps in the photolithography process. This consolidation decreases the total manufacturing time while preserving the ability to achieve precise pattern formation through optimized single-mask processes
3Manufacturing precision
If multiple mask processes are used in photolithography, then the manufacturing precision is improved, but the manufacturing cost is increased
Solution Approach 1:
The patent merges multiple insulation layer functions into a single layer, which directly reduces the number of expensive photolithography mask processes required. This approach lowers manufacturing costs by eliminating redundant processing steps while maintaining the precision needed for modern display device fabrication
4Reliability
If insulation layers are separately optimized for transistors and capacitors, then the reliability is improved, but the device complexity is increased
Solution Approach 1:
While maintaining a unified insulation layer structure, the patent enables separate optimization of different regions within the layer for transistor and capacitor functions. This segmentation approach allows tailored dielectric properties in different areas, improving signal transmission reliability without requiring entirely separate layer structures for each component type
Data Source
AI summary
A TFT array substrate including: a thin-film transistor including an active layer, gate, source and drain electrodes, a first insulation layer between the active layer and the gate electrode, and a second insulation layer between the gate and the source and drain electrodes; a pixel electrode on the first and second insulation layers, and connected to one of the source and drain electrodes; a capacitor including a first electrode on the same layer as the gate electrode, a second electrode formed of the same material as the pixel electrode, a first protection layer on the second electrode, and a second protection layer on the first protection layer; a third insulation layer between the second insulation layer and the pixel electrode, and between the first electrode and the second electrode; and a fourth insulation layer covering the source and drain electrodes and the second protection layer, and exposing the pixel electrode.