Superjunction Semiconductor Termination Region Field Stress Management
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Solution Overview
Problem
Power MOSFET devices with superjunction structures face challenges in achieving low on-resistance and high breakdown voltage simultaneously, as high voltages can damage the field oxide in the termination region, degrading the device's reliability.
Innovation Solution
A superjunction semiconductor device is designed with a termination region that includes a lower charge balance region of P-type conductivity and an upper charge balance region of N-type conductivity, forming a P-N junction to distribute electric field stress, preventing damage to the field oxide and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If dopant concentrations of P-type and N-type regions in the alternating conductivity type drift layer are decreased to increase breakdown voltage, then breakdown voltage is improved, but the field oxide is damaged by high voltage applied to the termination region, degrading reliability
Solution Approach 1:
The termination region is segmented into multiple sub-regions with alternating conductivity types (P-type and N-type charge balance regions) arranged in a pattern. This segmentation allows the electric field to be distributed across multiple interfaces, reducing the stress on any single field oxide region while maintaining high breakdown voltage capability.
Solution Approach 2:
Different regions of the termination structure are assigned different conductivity types and doping concentrations tailored to their specific functions. The charge balance regions have locally optimized properties to manage electric field distribution, while the field oxide regions are positioned where electric field stress is minimized, allowing each part to perform optimally without compromising overall reliability.
2Power
If a superjunction structure with alternating conductivity type drift layer is used to achieve low on-resistance and high breakdown voltage, then electrical performance is improved, but the field oxide in the termination region is damaged by high voltage, degrading reliability
Solution Approach 1:
The termination region is divided into multiple alternating P-type and N-type charge balance regions, creating multiple depletion region interfaces. This segmentation distributes the high voltage stress across multiple locations rather than concentrating it in one area, protecting the field oxide from damage while preserving the low on-resistance and high breakdown voltage characteristics of the superjunction structure.
Solution Approach 2:
The alternating P-type and N-type charge balance regions act as intermediary structures between the active superjunction drift layer and the field oxide. These intermediary regions manage the electric field distribution, preventing direct high voltage stress from reaching the field oxide, thus protecting it while maintaining the electrical performance benefits of the superjunction structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves a high breakdown voltage while maintaining low on-resistance and improving reliability by effectively managing electric field stress across the termination region.
Implementation Method 1
a lower charge balance region disposed on the lower edge region, the lower charge balance region having a second conductivity type different from the first conductivity type, and an upper charge balance region disposed on the lower charge balance region, the upper charge balance region having the first conductivity type
Data Source
AI summary
In at least one general aspect, a method can include forming a plurality of first active pillars and a plurality of edge pillars in a first semiconductor layer including an active region and a termination region, and forming a second semiconductor layer on the first semiconductor layer. The method can include forming a plurality of second active pillars and a plurality of preliminary charge balance layers in the second semiconductor layer, and annealing the first and second semiconductor layers such that the plurality of first active pillars and the plurality of second active pillars are connected by diffusing impurities implanted into the plurality of first active pillars and the plurality of second active pillars.