ESD Trigger Circuit with Time Multiplexed Signals
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Solution Overview
Problem
Conventional ESD protection mechanisms fail to effectively protect integrated circuits against a broad range of ESD event severities, particularly the higher severity system level ESD events which can cause damage due to their faster rise time and higher peak currents.
Innovation Solution
The implementation of an ESD trigger circuit employing feed-forward time division multiplexing, which generates two signals for different ESD severities, allowing for timely and sustained activation of the ESD clamp to divert charge away from the circuit, using a combination of RC derivators, nFET and pFET components to manage the ESD current and voltage, and optimizing the trigger logic to handle both HBM and system level ESD events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection mechanisms are used, then the circuit is protected against standard ESD events, but the protection is insufficient against higher severity system level ESD events with faster rise time and higher peak currents
Solution Approach 1:
The ESD trigger circuit is segmented into multiple independent trigger paths: a first trigger path with first trigger logic responsive to HBM ESD events, and a second trigger path with second trigger logic responsive to system level ESD events. Each path is optimized for its specific ESD severity range, allowing the circuit to effectively protect against both standard and high-severity ESD events without compromise
Solution Approach 2:
The ESD trigger circuit is designed with multi-functionality to handle multiple types of ESD events. The first and second trigger logic paths work together to provide universal protection against both HBM ESD events and system level ESD events, making the protection mechanism adaptable to a broad range of ESD severities rather than being limited to a single event type
2Speed
If the ESD clamp is activated quickly to protect against fast rise time ESD events, then protection response time is improved, but the activation duration may be insufficient to handle prolonged ESD events
Solution Approach 1:
The trigger logic is designed to dynamically adjust the ESD clamp activation characteristics based on the detected ESD event type. For system level ESD events with faster rise times, the circuit provides rapid activation. For HBM ESD events with longer durations, the circuit extends the activation duration. This dynamic adaptation allows the ESD clamp to optimize both response speed and activation duration according to the specific ESD event characteristics
Solution Approach 2:
The circuit changes operational parameters based on the ESD event detected. The first trigger logic generates an output signal with characteristics optimized for HBM ESD events, while the second trigger logic generates an output signal with characteristics optimized for system level ESD events. By changing the activation parameters (speed and duration) based on the event type, the circuit achieves effective protection across different ESD severities
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures rapid and prolonged activation of the ESD clamp to safely discharge ESD charges of varying severities, preventing damage to the integrated circuit by effectively managing both the speed and duration of ESD events, thus enhancing the overall ESD protection performance.
Implementation Method 1
RC derivators
Implementation Method 2
RC derivators
Implementation Method 3
nFET and pFET components to manage the ESD current and voltage
Data Source
AI summary
A circuit includes first logic that generates a first signal suitable to activate at least one ESD clamp in response to an electrostatic discharge (ESD) event having a first severity or a second severity higher than the first severity, and second logic that generates a second signal suitable to activate the ESD clamp in response to the ESD event having the second severity, the second signal time multiplexed with the first signal.