Self-Aligned Shared Contacts for Vertical Transport FETs
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Solution Overview
Problem
Conventional fabrication techniques face challenges in further scaling of integrated circuit devices, particularly in forming vertical transport field-effect transistors (VTFETs) due to difficulties in meeting key device metrics such as high density and performance, as they reach the limits of miniaturization.
Innovation Solution
The implementation of a replacement metal gate (RMG) process with self-aligned gate cut and self-aligned bottom source/drain contacts, enabling lateral dummy gate removal, work function metal fill, and isolation of all gates, which allows for the formation of shared gates between nFET and pFET regions, facilitating further device scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication techniques are used, then manufacturing simplicity is maintained, but device scaling and integration density are limited
Solution Approach 1:
A dummy gate structure is formed preliminarily before the actual gate definition to guide subsequent self-aligned processing steps. This preliminary structure enables precise alignment of contacts and gates without requiring complex lithographic alignment, thus improving device scaling while managing fabrication complexity
Solution Approach 2:
The self-aligned fabrication process uses the dummy gate and spacer structures to automatically define the positions of contacts and gates through sequential etching and deposition steps. The structures serve their own alignment function, eliminating the need for additional alignment marks or complex lithographic steps, thereby enabling better scaling without proportionally increasing process complexity
2Quantity of substance
If device size is reduced to increase density, then integration density improves, but manufacturing precision requirements become more stringent
Solution Approach 1:
The self-aligned process uses the dummy gate and spacer structures to automatically define contact positions through sequential etching steps. The physical presence of these structures guides the etch process to create precisely aligned features without requiring additional lithographic alignment, thereby achieving high integration density while maintaining manufacturing precision
Solution Approach 2:
The dummy gate is formed preliminarily to establish a reference structure that guides subsequent contact formation. This preliminary action creates a self-aligned reference that ensures precise positioning of contacts relative to gates, enabling higher density devices to be manufactured with controlled alignment precision
3Adaptability or versatility
If self-aligned shared contacts are implemented, then device integration is improved, but fabrication process complexity increases
Solution Approach 1:
Adjacent fins share common contacts formed through self-aligned processes. The dummy gate and spacer structures enable simultaneous formation of multiple contacts that serve adjacent devices, merging what would otherwise be separate fabrication steps into a unified self-aligned process, thereby improving integration while managing complexity
Solution Approach 2:
The dummy gate structure serves multiple functions: it acts as a placeholder during fabrication, provides alignment reference for contact formation, and enables self-aligned definition of contact positions. This multi-functionality allows the same structure to support shared contacts for multiple devices, improving integration density without adding proportionally to process complexity
Data Source
AI summary
A semiconductor structure includes a substrate, a bottom source/drain region disposed on a top surface of the substrate, and a plurality of fins disposed over a top surface of the bottom source/drain region. The fins provide vertical transport channels for one or more vertical transport field-effect transistors. The semiconductor structure also includes at least one self-aligned shared contact disposed between an adjacent pair of the plurality of fins. The adjacent pair of the plurality of fins includes a first fin providing a first vertical transport channel for a first vertical transport field-effect transistor and a second fin providing a second vertical transport channel for a second vertical transport field-effect transistor.