Self-Aligned Internal Spacers for GAA-FET Transistors
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Solution Overview
Problem
Existing methods for producing GAA-FET transistors face challenges in achieving precise alignment of internal spacers with external spacers, leading to variability in electrical characteristics due to unpredictable etching durations and dimensions, affecting channel length and transistor performance.
Innovation Solution
A method involving the use of a dummy gate and external spacers to self-align internal spacers through selective etching and oxidation, ensuring that internal spacers are aligned with external spacers and each other, maintaining consistent channel length and electrical insulation without modifying the channel dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If internal spacers are produced by etching without a stop layer, then the etching process is simpler, but the alignment between internal spacers and external spacers becomes imprecise
Solution Approach 1:
A stop layer is deposited on the nanowire surface before etching the internal spacers. This preliminary action creates a defined boundary that ensures precise alignment between the internal spacers and external spacers, eliminating the alignment variability caused by uncontrolled etching durations.
Solution Approach 2:
The stop layer acts as an intermediary element between the nanowire and the internal spacers. It provides a controlled interface that enables precise alignment while maintaining etching simplicity, serving as a reference plane for spacer formation.
2Productivity
If etching duration is extended to ensure complete cavity formation, then cavity formation is more complete, but alignment variability increases
Solution Approach 1:
The stop layer is deposited in advance to establish a predetermined etching depth reference. This allows the etching process to proceed completely while maintaining consistent alignment, as the stop layer provides a uniform termination point across all devices.
Solution Approach 2:
The stop layer provides a visual and physical feedback mechanism during etching, allowing the process to be stopped precisely when the internal spacers are formed to the correct depth, ensuring both complete cavity formation and consistent alignment.
3Productivity
If internal spacers are not precisely aligned with external spacers, then production is faster, but transistor electrical characteristics become variable
Solution Approach 1:
The stop layer is deposited before spacer formation to pre-establish the alignment reference. This preliminary action enables precise alignment to be achieved automatically during the etching process, ensuring reliable electrical characteristics without requiring additional alignment steps that would slow production.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise self-alignment of internal spacers, reducing variability in transistor characteristics and maintaining optimal electrical performance by ensuring accurate alignment and oxidation control, thereby enhancing the production of GAA-FET transistors.
Implementation Method 1
oxidising portions of the source and drain regions from the parts of one face of each of the source and drain regions revealed by, or accessible after, the removal of the second portion, the oxidised portions forming internal spacers
Data Source
AI summary
Method for producing a semiconductor device, comprising:producing a stack including a first crystalline semiconductor portion intended to form a channel and arranged on at least one second portion which can be selectively etched vis-à-vis the first portion,producing a dummy gate and external spacers,etching the stack, a remaining part of the stack under the dummy gate and the external spacers being conserved,producing source/drain by epitaxy from the remaining part of the stack;removing the dummy gate and the second portion,oxidizing portions of the source/drain from the parts of the source/drain revealed by the removal of the second portion, forming internal spacers,producing a gate electrically insulated from the source/drain by the external and internal spacers.