SOI MOS Transistor Power Switch Gate Isolation Thickness
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Solution Overview
Problem
SOI type semiconductor integrated circuits face challenges in power-source cutoff control due to differences in device isolation compared to bulk type MOS integrated circuits, leading to limitations in flexibility and efficiency of power consumption and operation performance.
Innovation Solution
The use of a mixture of SOI type MOS transistors with thicker gate isolation films for power switches, allowing for independent control of threshold voltage and gate voltage to reduce sub-threshold leak current and enhance current feeding capability, while allowing flexible layout without well isolation restrictions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a thicker gate isolation film is used for power switches to reduce sub-threshold leak current, then power consumption during cutoff is reduced, but ON-state resistance increases and current feeding capability deteriorates
Solution Approach 1:
The patent applies parameter changes by using different gate isolation film thicknesses for different transistor types. Specifically, thick film MOS transistors use a thicker gate isolation film (first thickness) to reduce sub-threshold leak current, while thin film MOS transistors use a thinner gate isolation film (second thickness, smaller than first) to maintain low ON-state resistance and high current feeding capability. This differential parameter assignment resolves the contradiction between reducing leakage and maintaining power delivery.
2Reliability
If well isolation is implemented in bulk type MOS integrated circuits to reduce junction leak, then device isolation is improved, but device complexity and manufacturing restrictions increase
Solution Approach 1:
The patent extracts the well isolation requirement from the SOI type MOS integrated circuit design. Unlike bulk type MOS circuits that require well isolation between power switches and thin-film MOS transistors, the SOI structure inherently provides sufficient isolation through its substrate architecture. This extraction of the well isolation requirement simplifies the device structure, reduces manufacturing restrictions, and eliminates the need for complex well isolation processes while maintaining adequate device isolation and reducing junction leak.
Data Source
AI summary
The semiconductor integrated circuit has so-called SOI type first MOS transistors (MNtk, MPtk) and second MOS transistors (MNtn, MPtn). The first MOS transistors have a gate isolation film thicker than that the second MOS transistors have. The first and second MOS transistors constitute a power-supply-interruptible circuit (6) and a power-supply-uninterrupted circuit (7). The power-supply-interruptible circuit has the first MOS transistors each constituting a power switch (10) between a source line (VDD) and a ground line (VSS), and the second MOS transistors connected in series with the power switch. A gate control signal for the first MOS transistors each constituting a power switch is made larger in amplitude than that for the second MOS transistors. This enables power-source cutoff control with a high degree of flexibility commensurate with the device isolation structure, which an SOI type semiconductor integrated circuit has originally.