Buried Gate Polysilicon Work Function Reduction for GIDL Control
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Solution Overview
Problem
Semiconductor memory devices face issues with short channel effects, increased parasitic capacitance, and deteriorated refresh characteristics due to the buried word line structure, which affects operational reliability and data transfer efficiency.
Innovation Solution
A line-type buried gate is formed by burying a non-operating gate with a polysilicon material to reduce the work function and Gate Induced Drain Leakage (GIDL), improving the refresh characteristics of the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional transistor with shortened channel length is used to reduce design rule, then the data storage capacity increases, but short channel effects and DIBL occur reducing operational reliability
Solution Approach 1:
The patent introduces a three-dimensional channel structure where the channel extends in the vertical direction rather than only horizontally. This dimensional change allows the channel length to be maintained in the vertical dimension even when the horizontal design rule is reduced, thereby preserving operational reliability while enabling higher data storage capacity through increased integration density.
Solution Approach 2:
The patent applies different impurity doping concentrations to different regions: lower concentration in the channel region to maintain refresh characteristics, and higher concentration in the source/drain regions to ensure proper transistor operation. This localized quality differentiation resolves the contradiction between maintaining reliability and achieving high capacity.
2Ease of operation
If a buried word line structure is used to reduce parasitic capacitance between bit line and word line, then the sense amplifier operating margin is improved, but GIDL characteristics are deteriorated and refresh characteristics are worsened
Solution Approach 1:
The patent extracts or removes the non-operating gate (isolation gate) that was causing GIDL effects and refresh characteristic deterioration. By eliminating this problematic component while maintaining the beneficial buried word line structure for parasitic capacitance reduction, the patent resolves the contradiction between sense amplifier performance and refresh characteristics.
Solution Approach 2:
The patent converts the potential harm of the buried gate structure by carefully controlling the presence and material composition of the non-operating gate. By removing or modifying this element, the harmful GIDL effect is eliminated while the beneficial parasitic capacitance reduction from the buried word line structure is preserved, thus improving both refresh characteristics and sense amplifier operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces GIDL and enhances the refresh characteristics of semiconductor devices, maintaining operational reliability and reducing parasitic capacitance, thereby improving the overall performance of semiconductor memory devices.
Implementation Method 1
burying a non-operating gate (isolation gate) with a polysilicon material to reduce a work function
Implementation Method 2
reduce Gate Induced Drain Leakage (GIDL) caused by the non-operating gate
Data Source
AI summary
In the semiconductor device, a line-type buried gate is formed by burying a non-operating gate (isolation gate) with a polysilicon material to reduce a work function and a Gate Induced Drain Leakage (GIDL) caused by the non-operating gate, resulting in improvement of refresh characteristics of the semiconductor device. Operating gates including a metal conductive material may be formed in a separate step.