Oxide Semiconductor Thin Film Transistor Gate Alignment
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Solution Overview
Problem
Thin film transistors using amorphous or polysilicon semiconductors face limitations in charge mobility and manufacturing complexity, and parasitic capacitance between the gate and source/drain electrodes can degrade their performance.
Innovation Solution
A thin film transistor design incorporating an oxide semiconductor with a channel region, source and drain regions, and a gate electrode, where the gate electrode is aligned with the channel region, and an insulating layer is used to reduce parasitic capacitance, and a buffer layer and reduction process are employed to enhance semiconductor material properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon is used as semiconductor material, then manufacturing process is simpler, but charge mobility is relatively low
Solution Approach 1:
The patent changes the material parameter from conventional silicon (amorphous or polysilicon) to oxide semiconductor, fundamentally altering the semiconductor's electrical properties to achieve higher charge mobility while maintaining compatibility with existing manufacturing processes
2Reliability
If polysilicon is used as semiconductor material, then charge mobility is relatively high, but manufacturing cost is increased and process is complicated
Solution Approach 1:
The patent changes the material parameter from polysilicon to oxide semiconductor, achieving comparable or superior charge mobility while eliminating the need for complex crystallization processes, thereby simplifying manufacturing
Solution Approach 2:
The patent employs oxide semiconductor materials that can be deposited using low-cost techniques such as sputtering or atomic layer deposition, replacing expensive polysilicon crystallization processes with more economical thin-film deposition methods
3Device complexity
If gate electrode overlaps source or drain electrode, then device structure is formed, but parasitic capacitance is generated which deteriorates transistor characteristics
Solution Approach 1:
The patent extracts or removes the overlapping portion of the gate electrode that would contact the source or drain electrodes, thereby eliminating the source of parasitic capacitance while preserving the essential transistor structure and function
Solution Approach 2:
The patent introduces a vertical dimension solution by forming an insulating layer that separates the gate electrode from the source/drain electrodes in the vertical direction, allowing horizontal overlap while preventing electrical interaction that causes parasitic capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the characteristics of the thin film transistor by reducing parasitic capacitance and enhancing charge mobility, resulting in better ON/OFF ratios and manufacturing efficiency.
Implementation Method 1
an insulating layer on the channel region... to reduce parasitic capacitance
Implementation Method 2
The oxide semiconductor can have higher electron mobility... than those of amorphous silicon and/or polysilicon
Implementation Method 3
performing a reduction process on the semiconductor pattern that is not covered by the insulating layer and the gate electrode to form a channel region covered by the gate electrode and to form a source region and a drain region
Data Source
AI summary
A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.