Semiconductor Capacitor Structure Sharing Common Electrode
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing capacitance value without increasing manufacturing costs or decreasing yield, particularly in capacitive elements used in analog circuits and flash memory, where the occupied area of these elements is large, affecting the overall semiconductor chip size.
Innovation Solution
A semiconductor device configuration featuring a capacitive element with a semiconductor layer, insulating layer, and conductor layer, where the semiconductor layer serves as a common electrode for both capacitive elements, and a p-type well region with a buried insulating layer, allowing for improved capacitance value per unit area without increasing manufacturing costs or reducing yield, achieved through a specific layer structure and manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the occupied area of the capacitive element is increased to improve capacitance value, then the capacitance value increases, but the manufacturing cost increases and manufacturing yield decreases
Solution Approach 1:
The patent merges two capacitive elements (first capacitive element with conductor layer as upper electrode, second capacitive element with p-type well region as lower electrode) to share the semiconductor layer as a common electrode. This integration allows both capacitive elements to be formed within a smaller occupied area, improving capacitance value without proportionally increasing manufacturing cost
Solution Approach 2:
The semiconductor layer serves multiple functions simultaneously: it acts as the lower electrode of the first capacitive element, the upper electrode of the second capacitive element, and provides electrical connection for both elements. This multi-functionality reduces the total number of required layers and occupied area, improving manufacturing efficiency
2Quantity of substance
If the occupied area of the capacitive element is increased to improve capacitance value, then the capacitance value increases, but the manufacturing yield decreases
Solution Approach 1:
The patent utilizes vertical stacking of layers (conductor layer over second insulating layer over semiconductor layer over first insulating layer over p-type well region) to increase capacitance value in the vertical dimension rather than expanding horizontally. This dimensional transition reduces occupied area while maintaining or improving capacitance, thereby improving manufacturing yield
3Area of stationary object
If the conductor layer and well region are made thinner to reduce occupied area, then the occupied area decreases, but depletion occurs reducing capacitance characteristics
Solution Approach 1:
The patent optimizes the thickness parameters of the conductor layer and well region to maintain sufficient capacitance characteristics while minimizing occupied area. By carefully controlling these dimensional parameters, the design achieves depletion prevention without excessive area occupation
Data Source
AI summary
This invention is to improve a performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a p-type well region formed in the semiconductor substrate, a first insulating layer formed over the p-type well region, a semiconductor layer formed over the first insulating layer, a second insulating layer formed over the semiconductor layer, and a conductor layer formed over the second insulating layer. A first capacitive element is comprised of the semiconductor layer, the second insulating layer, and the conductor layer, while a second capacitive element is comprised of the p-type well region, the first insulating layer, and the semiconductor layer, in which each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.