Semiconductor Super-Connect Interconnection for High-Speed Signal Integrity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed signal transmission over 10 Gbps in semiconductor devices is hindered by large parasitic capacitance between the signal pad and the semiconductor element interconnection, leading to unstable input-output and deteriorated signal quality.
Innovation Solution
The implementation of a semiconductor device with a super-connect interconnection structure, featuring a thick super-connect insulating layer and interconnection, and a smaller signal pad area compared to power and ground pads, which reduces parasitic capacitance through the use of a super-connect insulating layer with a thickness five or more times larger than standard layers and interconnections three or more times thicker than standard ones, combined with a process of forming slits in the signal pad to isolate its center section.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard interconnection structure is used, then the device complexity is low, but the signal quality deteriorates due to large parasitic capacitance at high speeds
Solution Approach 1:
The interconnection structure is segmented into multiple layers: element interconnection layer, top-layer element interconnection, super-connect interconnection layer, and bump layer. Each layer serves a specific function and is optimized independently, allowing the signal pad area to be reduced while maintaining overall structural integrity and reducing parasitic capacitance.
Solution Approach 2:
The patent transitions from a planar interconnection structure to a three-dimensional super-connect structure with thickness five or more times larger than standard layers. This vertical dimensionality change allows signal pads to be smaller while maintaining electrical performance, as the extended vertical path compensates for reduced horizontal area.
2Reliability
If the signal pad area is reduced, then the parasitic capacitance decreases, but the manufacturing precision requirements increase
Solution Approach 1:
The signal pad is designed with non-uniform area distribution, with the center section having a smaller area than the peripheral section. This local quality variation optimizes the balance between reducing parasitic capacitance and maintaining sufficient connection area for reliable manufacturing.
3Reliability
If a thick super-connect insulating layer is used, then the parasitic capacitance is reduced, but the device complexity increases
Solution Approach 1:
The thick super-connect insulating layer serves multiple functions: it provides electrical isolation between the element interconnection and super-connect interconnection, reduces parasitic capacitance through increased thickness, and supports the bump structure. This multi-functionality justifies the increased structural complexity.
Data Source
AI summary
A semiconductor device has an element interconnection 2, a top-layer element interconnection 4, a super-connect interconnection 10 and a bump 7. The element interconnection 2 is provided on a semiconductor substrate 1 through a plurality of insulating layers 50. The top-layer element interconnection 4 is formed above the element interconnection 2 by using a substantially equivalent process equipment. The super-connect interconnection 10 is provided on the top-layer element interconnection 4 through a super-connect insulating layer 9 having a thickness five or more times larger than that of the insulating layer 5, and has a thickness three or more times larger than that of each the element interconnection 2 and the top-layer element interconnection 4. The bump 7 is formed on the super-connect interconnection 10. The top-layer element interconnection 4 has a signal pad 4s, a power source pad 4v and a ground pad 4g. An area of the signal pad 4s is smaller than each area of the power source pad 4v and the ground pad 4g.