Nanoparticle-Masked Discrete Floating Gate Memory
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing storage capacity within a reduced substrate area, as traditional charge storage elements, such as conductive floating gates, are inefficient in scaling down and require high programming voltages, leading to increased power consumption.
Innovation Solution
The use of nanostructure-based charge storage regions, where nanoparticles or nanodots act as masks to pattern discrete semiconducting or conducting floating gate regions, allowing for reduced programming voltages and smaller device dimensions, enabling more efficient and compact memory cell design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional conductive floating gates are used for charge storage, then the memory device can store charge effectively, but the device dimensions cannot be scaled down efficiently and programming voltages are high leading to increased power consumption
Solution Approach 1:
The continuous floating gate layer is segmented into discrete floating gate regions by using nanoparticle masks to define isolated charge storage areas. This segmentation enables smaller device dimensions while maintaining effective charge storage capability, as each nanoparticle-defined region acts as an independent storage element that requires lower programming voltages compared to traditional extended floating gates
Solution Approach 2:
The invention changes the physical state and dimensions of the floating gate structure by defining it through nanoparticle masks rather than continuous lithographic patterns. This parameter change in structure definition enables reduced programming voltages and lower power consumption while achieving scalable device dimensions
2Manufacturing precision
If traditional lithography methods are used to pattern floating gate layers, then the manufacturing process is straightforward, but the minimum feature size is limited and storage capacity per area cannot be increased sufficiently
Solution Approach 1:
The invention transitions from two-dimensional lithographic patterning to three-dimensional nanoparticle-based masking, where nanoparticles provide precise spatial definition in multiple dimensions. This dimensional change enables feature sizes below traditional lithography limits while increasing storage capacity per unit substrate area through more precise and dense feature definition
3Stability of the object's composition
If continuous floating gate layers are used, then the charge storage is uniform across the device, but the device area is larger and scaling is limited
Solution Approach 1:
The continuous floating gate layer is divided into discrete segments defined by nanoparticle masks, creating uniformly distributed charge storage regions across the device area. This segmentation maintains charge storage uniformity through regular nanoparticle spacing while reducing overall device area by eliminating continuous material and enabling higher density integration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power/current consumption and enables scaling to smaller dimensions, enhancing storage capacity within a given area while maintaining efficient memory device performance.
Implementation Method 1
etching the floating gate layer using the plurality of nanodots as a mask to form a floating gate region comprising a plurality of discrete semiconducting or conducting regions
Data Source
AI summary
A memory cell including a control gate located over a floating gate region. The floating gate region includes discrete doped semiconducting or conducting regions separated by an insulator and the discrete doped semiconducting or conducting regions have a generally cylindrical shape or a quasi-cylindrical shape.