3D Cross-Point Memory Decoder Segmentation
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Solution Overview
Problem
In 3D cross-point memory arrays, the area and complexity of decoders increase with the number of memory cells, leading to larger and more complex decoding circuits, which is undesirable.
Innovation Solution
The proposed solution involves a 3D cross-point memory array with shared decoder and driver circuitry that applies common operational voltages to multiple access lines, reducing the decoding burden by grouping access lines into sets rather than treating each line independently, thereby simplifying the decoding process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells is increased by stacking more memory arrays or increasing the number of levels, then the storage capacity is improved, but the area and complexity of decoders increase
Solution Approach 1:
The memory array is divided into multiple banks, with each bank having its own dedicated decoder. This segmentation allows the decoding function to be distributed across multiple smaller decoder units rather than requiring one large complex decoder for the entire array, thereby reducing the complexity and area of individual decoder circuits while maintaining the ability to address all memory cells in the stacked architecture.
2Quantity of substance
If the number of memory cells is increased by stacking more memory arrays or increasing the number of levels, then the storage capacity is improved, but the area occupied by decoders increases
Solution Approach 1:
The memory array is divided into multiple banks, with each bank having its own dedicated decoder. This segmentation allows the decoding function to be distributed across multiple smaller decoder units rather than requiring one large complex decoder for the entire array, thereby reducing the area occupied by individual decoder circuits while maintaining the ability to address all memory cells in the stacked architecture.
Solution Approach 2:
The patent utilizes vertical stacking of memory arrays in the third dimension to increase storage capacity without proportionally increasing the planar area of decoders. By organizing memory cells in multiple stacked levels and dividing them into banks, the decoder area is decoupled from the total storage capacity growth, allowing high-density 3D memory structures with manageable decoder footprints.
Data Source
AI summary
An integrated circuit includes a three-dimensional cross point memory array having M levels of memory cells disposed in cross points of N first access line layers and P second access line layers. The integrated circuit further comprises first and second sets of first access line drivers. The first set of first access line drivers is operatively coupled to apply a common first operational voltage to selected first access lines in odd first access line layers. The second set of first access line drivers is operatively coupled to apply the common first operational voltage to selected first access lines in even first access layers. A plurality of sets of second access line drivers is operatively configured to apply a second operational voltage to selected second access lines in selected second access line layers.