Read-Only Memories TRIZ Cases

Controller reads adjacent pages to adjust threshold voltage distribution, resolving bit error correction limits in flash memory.

A NAND flash memory reading method applies positive voltage to a source line and adjacent bit line to detect negative threshold voltages.

A storage medium management device automatically updates congenital defective block identification during replacement operations.

A memory device uses a precharge mechanism to set the evaluation circuit output voltage before bit line charging.

Continuous word line voltage application eliminates discharge cycles during memory cell programming operations.

Segmenting the array into banks distributes decoding functions across smaller units, resolving the trade-off between storage capacity and decoder complexity.

Semiconductor controlled rectifier maintains low on-resistance state during efuse programming, reducing power dissipation and protecting thin oxide transistors.

A memory managing circuit performs extra reads in retention margins to detect failure bits.

Source side sensing circuitry detects cell currents while minimizing leakage interference that corrupts drain side measurements.

A NOR flash memory discharging circuit maintains constant high voltage to generate erase potential during operations.

Hierarchical segmented drivers reduce word line resistance and decoder area, enabling reliable data writing in high-density phase change memory arrays.

A storage device adjusts pass voltages applied to unselected word lines based on the selected cell position.

A source follower sense amplifier buffers bit line voltage to detect current flow through NAND strings.

A solid state drive reorganizes calibration tasks across multiple memory planes to reduce read latency.

A NAND flash memory control unit applies position-dependent word line voltages to manage electron storage across cell strings.

Split ground selection lines and pass transistors reduce word line loading in 3D NAND flash memory devices.

Segmented stacked gates raise channel potential to cut off non-selected cells, preventing false writes and improving boost efficiency.

Varying drain-side select gate layer thickness stabilizes threshold voltage in semiconductor storage devices.

Comparing voltage window differences against thresholds detects imminent read failures from cell wear, preventing false passes.

Segmenting word line layers across heterogeneous planes resolves the trade-off between increasing storage capacity and maintaining read latency performance.

A write circuit controls power supply voltages to lower negative side potential before adjusting positive side levels.

Shared virtual ground lines reduce device area and design complexity while maintaining low voltage operation for high-density storage.

Segmented local word lines apply higher pass voltages to unselected areas to isolate channels and prevent program disturbances in nonvolatile memory devices.

A memory device reduces peak current by precharging channel regions through a common source line.

Voltage modifying data adjusts zener diode potentials to correct uneven withstand voltages, ensuring uniform output during memory operations.

A drain-side wordline voltage boosting mechanism adjusts pass-through potentials during memory cell programming operations.

A read voltage threshold adjustment system dynamically compensates for storage cell degradation by tracking bias deviations.

Segmented wordline scans prevent unnecessary block folding and reduce system latency while maintaining data integrity during read operations.

Shared voltage node prevents floating of unselected local word lines, reducing NMOS transistor count and decoder area.

Segmented voltage application reduces Gate Induced Drain Leakage stress during channel boosting, preventing soft programming errors.

A semiconductor memory device stores management data redundantly across multiple pages to enable accurate reading operations.

A semiconductor memory device controller executes erase sequences for target blocks across multiple planes.

Interleaving status bits before and after data enables detection of incomplete writes caused by power fluctuations, preserving data integrity.

Replacing flip-flops with N/2 master-slave latch pairs reduces layout area and power consumption while maintaining scan-testability.

Voltage history monitoring differentiates momentary from ongoing power drops, preventing premature bad-block retirement and preserving storage capacity.

Segmenting bit lines with intermediary sense amplifiers reduces capacitance and power dissipation while maintaining chip area efficiency.

Standard cell PRD memory bit slices use program selectors to reduce programming current.

A system measures threshold voltage distribution across nonvolatile memory cells to dynamically adjust read compare voltages.

A read-only memory architecture connects transistor junctions to logic zero in idle states to eliminate sub-threshold leakage currents.

A nonvolatile memory controller executes reprogramming refresh processes using specific voltage corrections to stabilize threshold distributions.

Grouping program states into multiple program groups enables sequential programming, reducing program time while maintaining data retention.

Shield conductive lines apply compensation voltages to floating bitlines, neutralizing parasitic potential and preventing involuntary programming.

Measuring control line resistance before data read identifies defects that standard verification misses, preventing uncorrectable errors.

A memory array couples flash and random access memory through a management module that transfers data between the two storage types.

Dynamic read voltage adjustment compensates for program disturbance shifts in threshold voltages, reducing bit-error rates and maintaining data integrity.

A flash memory controller reads adjacent pages and applies weighting values to raw data signals.

Inter-chip wiring transfers discharged electric charge between NAND flash devices to reduce peak current and lower consumption current.

Three-dimensional flash memory cell strings protrude horizontally to expand the cross-sectional area of the channel layer.

A control means acquires smart verify programming voltage from a sampling string to program memory cells.

Controller identifies hot data by read frequency and transfers it to SLC blocks, preventing read disturbances in MLC memory.