Low Leakage ROM Architecture Using Equipotential Transistor Biasing
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Solution Overview
Problem
Existing ROM architectures experience high leakage current due to voltage drops between transistor junctions, which is a dominant component of total ROM leakage, and existing solutions either result in slow ROMs or are not feasible due to standard architecture constraints.
Innovation Solution
A ROM architecture where the gate, drain, source, and bulk of a transistor are electrically connected to logic zero in the idle state, minimizing junction and sub-threshold leakage current, and a pre-charging method using multiple transistors and sensing units to control bit lines and word lines for efficient read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If N-MOS transistor is used with bit line charged to highest potential, then read operation is enabled, but leakage current increases due to voltage drop between drain and source
Solution Approach 1:
The patent connects the source of the N-MOS transistor to the bulk potential through a dedicated connection, ensuring that the source-bulk junction remains at zero potential difference. This equipotential connection eliminates junction leakage while allowing the drain-bit line voltage drop necessary for read operations to proceed normally.
2Loss of energy
If virtual ground is used at source of transistor, then leakage current is reduced, but junction leakage still exists due to voltage potential between source-bulk and drain-bulk junctions
Solution Approach 1:
The patent establishes an equipotential connection between the source and bulk by directly connecting them through a low-impedance path. This ensures that no voltage potential develops between source-bulk junction, eliminating the junction leakage that persists in virtual ground configurations where source and bulk are not held at the same potential.
3Loss of energy
If P-MOS architecture is used to reduce leakage current, then leakage is minimized, but ROM becomes very slow or requires very large size
Solution Approach 1:
The patent changes the electrical parameters of the N-MOS transistor by holding the source-bulk voltage at zero (VB-S = 0) while allowing normal drain-source voltage operation. This parameter control eliminates the need to switch to P-MOS technology, maintaining fast N-MOS switching speeds while achieving low leakage through optimized biasing conditions.
4Power
If transistor size is increased to compensate for P-MOS slowness, then current is increased, but ROM size becomes very large
Solution Approach 1:
The patent achieves the desired current levels by optimizing the biasing parameters of standard-sized N-MOS transistors rather than increasing device dimensions. By maintaining source-bulk equipotentiality, the transistor operates with minimal leakage while preserving its original drive current capability, avoiding the area penalty of oversized devices.
Data Source
AI summary
Read only memory (ROM) with minimum leakage is provided. The ROM includes a read only memory array. The read only memory array includes a first transistor, wherein a drain, a source, a gate, and a bulk of the first transistor is electrically connected to a logic zero in the idle state for ensuring zero junction and sub-threshold leakage current. Another ROM includes a first transistor comprising a gate, electrically connected to a word line to provide a read signal, a drain, electrically connected to a main bit line through a second transistor. The second transistor includes a gate, electrically connected to a first decoding circuit, a drain, electrically connected to the main bit line. A first reference bit line is electrically connected to a drain of a third transistor, wherein gate of the third transistor is electrically connected to a second decoding circuit for generating a stop read signal. A second reference bit line, electrically connected to the first decoding circuit through a first sensing unit for generating a stop pre-charge signal. Further, a reference word line is electrically connected to a gate of a fourth transistor.