Flash Memory Discharging Circuit for Reduced Erase Time
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Solution Overview
Problem
NOR flash memory devices have a slow erase operation speed due to the reduction in operational voltage, which decreases the current capacity of MOS transistors, leading to longer erase times.
Innovation Solution
A discharging circuit that maintains a high voltage constant irrespective of power voltage variations, generating an erase voltage during the erase operation and discharging it during the recovery period using a PMOS and NMOS transistor configuration, ensuring consistent current capacity for efficient erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If operational voltage is reduced, then power consumption is decreased, but erase operation speed deteriorates due to decreased current capacity of MOS transistors
Solution Approach 1:
The patent implements dynamic voltage control where the wordline voltage is adjusted based on the operational phase. During erase operation, high voltage is applied to maintain fast erase speed, while during recovery period, voltage is reduced to save power. This dynamic adjustment resolves the contradiction between power consumption and erase speed by applying high voltage only when necessary for the erase operation itself.
Solution Approach 2:
The patent changes the voltage parameter dynamically during different phases of the erase operation. The wordline voltage transitions from a reduced level during normal operations to a high level during the erase operation to ensure fast performance, then returns to reduced level during recovery. This parameter change strategy allows the system to achieve fast erase speed when needed while maintaining low power consumption during other phases.
2Productivity
If high voltage is applied during erase operation, then erase speed is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic high voltage application only during the erase operation phase, while maintaining low voltage during recovery and other phases. This periodic action pattern ensures that high power consumption occurs only during the brief erase operation window, while the majority of the time the device operates at low power, thus resolving the contradiction between erase speed and overall power consumption.
Solution Approach 2:
The patent prepares the high voltage supply in advance during the recovery period at low power levels, then quickly switches to high voltage only when the erase operation is initiated. This preliminary preparation allows the system to maintain low power consumption while being ready to deliver high speed erase performance when required, without continuously consuming high power.
3Use of energy by stationary object
If erase voltage is not discharged during recovery period, then power consumption is reduced, but erase operation reliability deteriorates
Solution Approach 1:
The patent implements an automatic voltage discharge mechanism during the recovery period that operates without external intervention. The circuit automatically detects the end of the erase operation and initiates voltage discharge to prepare for the next operation, ensuring reliability while maintaining low power consumption during the recovery phase. This self-service approach resolves the contradiction by automatically managing the voltage discharge needed for reliability without requiring continuous high power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces erase time by maintaining consistent current capacity and preventing the increase in erase time and decrease in speed associated with power voltage drops, as demonstrated by an erase recovery time of less than 10 us even at low power voltage.
Implementation Method 1
During an erase operation for the NOR flash memory cell, a high voltage gap is established between the control gate and substrate (or bulk material), which induces a so-called Fowler-Nordheim tunneling effect to release the electrons accumulated on the floating gate.
Data Source
AI summary
A NOR flash memory device comprises a memory cell array, a row selection circuit adapted to drive wordlines in the memory cell array with a wordline voltage during an erase operation, and an erase voltage generating circuit adapted to generate an erase voltage as the wordline voltage during the erase operation. The erase voltage generating circuit includes a discharging circuit receiving a high voltage that is regularly maintained irrespective of variations in a power voltage, and discharging the erase voltage supplied from the wordline during an erasing recovery period of the erase operation.