Non-volatile Memory Controller Interleaved Status Bit Verification

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Solution Overview

Problem

Existing data processing devices that emulate EEPROM using a portion of flash memory face issues with data corruption due to power fluctuations and asynchronous resets, as the storage of status bits is prone to failure during such events.

Innovation Solution

A method is implemented where status bits are interleaved with data storage in a non-volatile memory, allowing for the comparison of first and second status bits to determine if data was properly stored, and data consolidation and selective erasure are performed to manage memory space effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a portion of flash memory is used to emulate EEPROM for storing configuration information, then the cost of the electronic device is reduced, but data corruption occurs during power fluctuations and asynchronous resets

Engineering Contradiction:
Improvecost reductionVSAvoiddata integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The system performs preliminary actions by storing a first status bit before writing data and a second status bit after writing data. This preliminary status bit storage creates a verification mechanism that detects incomplete write operations caused by brown-outs, allowing the system to identify and discard corrupted data while preserving valid data.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback by comparing the first and second status bits to determine whether data was successfully written. This feedback mechanism provides information about the completeness of the write operation, enabling the system to respond appropriately by either using the written data or restoring from a previous valid state.

Inventive Principle:
Principle #23Feedback

2Device complexity

If status bits are stored sequentially with data in flash memory, then the storage process is simple, but brown-outs during data storage cause corruption of the mirrored information

Engineering Contradiction:
Improvestorage process simplicityVSAvoidinformation integrity
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The status information is segmented into multiple separate status bits stored at different locations in the flash memory. The first status bit is stored before data writing, and the second status bit is stored after data writing. This segmentation allows independent verification of each write phase, enabling detection of partial writes without requiring complex error correction codes.

Inventive Principle:
Principle #1Segmentation

3Reliability

If interleaved status bit storage is implemented to detect corruption, then data integrity is improved, but the storage process becomes more complex

Engineering Contradiction:
Improvedata integrityVSAvoidstorage process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by storing status bits at specific locations within the flash memory record structure. Each status bit is placed at a defined position (before and after data) to provide localized verification points. This approach maintains simplicity by using basic read/write operations at specific addresses rather than implementing complex error correction algorithms across the entire data structure.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8271719B2Non-volatile memory controller device and method therefor
Publication Date: 2012.09.18 NXP USA INC
  • US8271719B2 patent drawing
  • US8271719B2 patent drawing
  • US8271719B2 patent drawing

AI summary

A method of storing information at a non-volatile memory includes storing a status bit prior to storing data at the memory. A second status bit is stored after storing of the data. Because the storage of data is interleaved with the storage of the status bits, a brownout or other corrupting event during storage of the data will likely result in a failure to store the second status bit. Therefore, the first and second status bits can be compared to determine if the data was properly stored at the non-volatile memory.