NVM Imminent Read Failure Detection via Error Voltage Window Sweeps
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Solution Overview
Problem
Existing non-volatile memory (NVM) systems face challenges in detecting imminent read failures due to uncorrectable errors caused by wear, which can lead to catastrophic results in sensitive applications, as current error correction code (ECC) routines may inaccurately detect or fail to correct multiple-bit errors.
Innovation Solution
The method involves running a diagnostic mode at different times to determine high/low error voltage windows using high/low read voltage sweeps, comparing the differences in these windows to a voltage difference threshold value to assess wear rates, and indicating imminent read failures if the wear is deemed unacceptable.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC routines are used to correct errors in NVM cells, then data reliability is improved, but the system cannot detect imminent read failures caused by unacceptable wear rates
Solution Approach 1:
The patent applies preliminary action by conducting diagnostic reads at multiple voltage levels before actual read failures occur. The system performs low voltage sweeps and high voltage sweeps to identify error voltage windows that indicate unacceptable wear rates, allowing proactive detection of imminent read failures before they impact data reliability
Solution Approach 2:
The patent introduces an intermediary diagnostic mode that mediates between normal read operations and failure detection. This diagnostic mode uses voltage sweeps and error voltage window analysis as an intermediate measurement mechanism to assess wear rates without disrupting normal data read operations, enabling detection of imminent failures while maintaining data reliability
2Difficulty of detecting and measuring
If diagnostic modes with voltage sweeps are implemented to detect wear rates, then imminent read failure detection is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the diagnostic mode to serve multiple functions: it performs wear rate assessment, identifies error voltage windows, and detects imminent read failures all within a single diagnostic framework. The voltage sweep mechanism serves both as a measurement tool and as a stress test for the memory cells, reducing the need for separate diagnostic procedures
Solution Approach 2:
The patent utilizes parameter changes by varying read voltage levels during diagnostic operations. The system performs sweeps at multiple voltage points (low voltage, normal voltage, high voltage) to map the error voltage window, using parameter variation as a diagnostic tool rather than adding complex hardware, thus improving detection capability while managing device complexity
Data Source
AI summary
Methods and systems are disclosed for imminent read failure detection based upon changes in error voltage windows for non-volatile memory (NVM) cells. In certain embodiments, data stored within an array of NVM cells is checked at a first time using a diagnostic mode and high/low read voltage sweeps to determine a first error voltage window where high/low uncorrectable errors are detected. Stored data is then checked at a second time using the diagnostic mode and high/low read voltage sweeps to determine a second error voltage window where high/low uncorrectable errors are detected. The difference between the error voltage windows are then compared against a voltage difference threshold value to determine whether or not to indicate an imminent read failure condition. An address sequencer, error correction code (ECC) logic, and a bias generator can be used to implement the imminent failure detection.