Flash Memory Programming Method Reducing GIDL Stress
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Solution Overview
Problem
Flash memory devices face inefficiencies in boosting operations and are prone to soft programming errors due to Gate Induced Drain Leakage (GIDL), which affects programming accuracy and device reliability.
Innovation Solution
A programming method for flash memory devices that involves applying a first pass voltage to selection and non-selection word lines, followed by a local voltage to disconnect channels, and a second pass voltage to boost selection channels, while maintaining lower voltages on non-selection channels to reduce stress and prevent GIDL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a pass voltage is applied to both selection and non-selection word lines during programming, then channel formation is achieved, but boosting efficiency is insufficient and stress is increased
Solution Approach 1:
The patent segments the word lines into selection word lines and non-selection word lines, applying different voltage levels to each group. Selection word lines receive the full pass voltage for boosting, while non-selection word lines receive a reduced voltage level, thereby improving boosting efficiency for target cells while reducing overall stress on the memory array.
Solution Approach 2:
The patent implements local quality by differentiating the voltage treatment between selection and non-selection word lines. The selection word lines receive higher voltage for effective channel boosting in the target region, while non-selection word lines receive lower voltage to minimize stress in non-target regions, achieving localized optimization of both efficiency and stress reduction.
2Manufacturing precision
If a high pass voltage is applied to boost channels, then programming accuracy is improved, but Gate Induced Drain Leakage increases causing soft programming errors
Solution Approach 1:
The patent segments the voltage application by distinguishing between selection and non-selection word lines. High pass voltage is applied only to selection word lines where channel boosting is needed for programming accuracy, while non-selection word lines receive reduced voltage, thereby minimizing Gate Induced Drain Leakage in non-target regions and preventing soft programming errors.
Solution Approach 2:
The patent applies local quality by concentrating the high voltage stress only where needed for programming accuracy (selection word lines) while protecting non-target regions (non-selection word lines) from excessive voltage. This localized approach maintains programming accuracy in the target area while suppressing GIDL effects that would cause soft errors in other areas.
3Stability of the object's composition
If pass voltage is applied to all word lines, then channel formation is complete, but stress on memory cells is maximized
Solution Approach 1:
The patent segments the word line population into selection and non-selection groups, applying full pass voltage only to selection word lines for necessary channel formation, while non-selection word lines receive reduced voltage. This maintains adequate channel formation in target regions while significantly reducing overall stress on the memory cell array.
Solution Approach 2:
The patent applies partial action by providing full pass voltage only to the extent necessary for selection word lines (where channel formation is critical) while applying reduced voltage to non-selection word lines. This partial application of high voltage maintains sufficient channel formation for programming while avoiding excessive stress on the entire memory array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances boosting efficiency, decreases stress caused by pass voltage application, and minimizes the likelihood of soft programming errors, thereby improving the reliability and accuracy of memory cell programming.
Implementation Method 1
a tunnel dielectric layer, a charge trapping layer, a blocking dielectric layer, and a control gate. Electrons may be trapped in the charge trapping layer by a tunneling process
Data Source
AI summary
Provided is a programming method in a flash memory device. The programming method applies a first pass voltage to a selection word line and a non-selection word line, applies a local voltage to the non-selection word line, applies a second pass voltage to the selection word line, and applies a programming voltage to the selection word line.