Asymmetric Select Gate Thickness for Semiconductor Storage

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Solution Overview

Problem

Existing semiconductor storage devices face fluctuations in the threshold voltage of drain-side select transistors due to variations in the manufacturing process, leading to inconsistent performance during write and erase operations.

Innovation Solution

The semiconductor storage device design features conductive layers with varying Z-direction lengths, where the lengths of the first two drain-side select gate layers (LZSGD1 and LZSGD2) are greater than the third (LZSGD3), controlling the electron distribution and cutoff position to stabilize the threshold voltage, thereby reducing fluctuations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the drain-side select gate layers have uniform thickness, then the manufacturing process is simpler, but the threshold voltage of drain-side select transistors fluctuates due to manufacturing variations

Engineering Contradiction:
Improvethreshold voltage stabilityVSAvoidconductive layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies asymmetry by setting different thicknesses for different drain-side select gate layers. Specifically, the first drain-side select gate layer has a first thickness and the second drain-side select gate layer has a second thickness that is greater than the first thickness. This asymmetric design compensates for manufacturing process variations and stabilizes the threshold voltage of drain-side select transistors, resolving the contradiction between reliability and manufacturing simplicity.

Inventive Principle:
Principle #4Asymmetry

2Manufacturing precision

If additional impurity implantation is used to control threshold voltage, then the threshold voltage can be precisely controlled, but the manufacturing process becomes more complex and costly

Engineering Contradiction:
Improvethreshold voltage controlVSAvoidmanufacturing process
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent changes the physical parameter of conductive layer thickness to control threshold voltage. By setting the second drain-side select gate layer to have a greater thickness than the first drain-side select gate layer, the patent achieves precise threshold voltage control without requiring additional impurity implantation processes. This approach maintains manufacturing simplicity while achieving the desired electrical characteristics.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively stabilizes the threshold voltage of drain-side select transistors, reducing variations and improving operational reliability without the need for additional impurity implantation, thus simplifying the manufacturing process and reducing costs.

Implementation Method 1

a charge storage film interposed between the conductive layers and the semiconductor layer

Methodology Applied
Scientific EffectCharge storage: Capacitance

Data Source

PatentUS20230328994A1Semiconductor storage device
Publication Date: 2023.10.12 KIOXIA CORP
  • US20230328994A1 patent drawing
  • US20230328994A1 patent drawing
  • US20230328994A1 patent drawing

AI summary

According to one embodiment, a semiconductor storage device includes word lines stacked in a first direction with bit lines above word lines in the first direction. A plurality of select gate lines are between the word lines and the bit lines in the first direction, and a semiconductor layer extends through the word lines and select gate lines. A charge storage film is between the word lines and the first semiconductor layer. The plurality of select gate lines includes a first select gate line closest to the word lines with a first thickness and second select gate line between the first select gate line and the bit lines with a second thickness. The first thickness is less than the second thickness.