Nonvolatile Memory Decoder Level Shifting Floating Prevention
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Solution Overview
Problem
Conventional NOR-type flash memory decoders face complexity and size issues due to the need to prevent floating of unselected local word lines, which increases the number of NMOS transistors and signal lines required, complicating the decoder structure and increasing its area.
Innovation Solution
A decoder design that includes a level shifter producing opposite voltages for selected and unselected global word lines, with local word line drivers using PMOS and NMOS transistors to drive local word lines to a common voltage when unselected, reducing the complexity and size by minimizing NMOS transistors and signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional decoder design is used to prevent floating of unselected local word lines, then floating prevention is achieved, but decoder complexity and area increase due to additional NMOS transistors and signal lines
Solution Approach 1:
The patent extracts the floating prevention function from the traditional per-word-line NMOS transistor approach and implements it through a shared common voltage node that serves all local word lines. This removes the need for individual NMOS transistors at each word line intersection, significantly reducing decoder complexity while maintaining floating prevention.
Solution Approach 2:
The patent merges the floating prevention function into a common voltage node that is shared across multiple local word lines. Instead of having separate control mechanisms for each word line, the common node collectively manages the voltage level for all unselected local word lines, reducing the number of signal lines and transistors required.
2Reliability
If conventional decoder design with multiple NMOS transistors is used, then floating prevention is achieved, but decoder area increases
Solution Approach 1:
The patent merges the floating prevention function into a common voltage node that is shared across multiple local word lines. Instead of having separate control mechanisms for each word line, the common node collectively manages the voltage level for all unselected local word lines, reducing the number of signal lines and transistors required.
Solution Approach 2:
The common voltage node serves multiple functions: it prevents floating of unselected local word lines, provides a reference voltage level, and reduces the overall decoder area. This multi-functional approach eliminates the need for dedicated floating prevention circuitry at each word line intersection.
3Reliability
If more signal lines are added to control NMOS transistors for floating prevention, then floating control is improved, but signal line complexity and area increase
Solution Approach 1:
The patent merges the floating prevention function into a common voltage node that is shared across multiple local word lines. Instead of having separate control mechanisms for each word line, the common node collectively manages the voltage level for all unselected local word lines, reducing the number of signal lines and transistors required.
Data Source
AI summary
A decoder for a nonvolatile memory device includes a level shifter configured to produce a first voltage at an output thereof responsive to a first state of a global word line and to produce a second voltage at the output responsive to a second state of the global word line. The decoder further includes a plurality of local word line drivers, each having an input coupled to the output of the level shifter, the respective local word line drivers configured to drive respective local word lines responsive to voltages on respective partial word lines when the output of the level shifter is at the first voltage and to drive the respective local word lines to a common voltage when the output of the level shifter is at the second voltage. The first state of the global word line may generate a third voltage at an input of the level shifter, the second state of the global word line may generate a fourth voltage at the input of the level shifter, and the first and second voltages may have opposite polarities.