NAND Flash Memory Cell Stacked Gate Structure for Boost Efficiency
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Solution Overview
Problem
Conventional NAND-type flash memory experiences decreased boost efficiency and incorrect data writing due to inability to cut off channel potential in memory cells, leading to false writes, especially when data is written near the source side.
Innovation Solution
The semiconductor storage device employs memory cell transistors with a stacked gate structure including a charge accumulation layer and a control gate, where the threshold voltage for '0' data is set higher for memory cells not adjacent to the selection transistor, allowing for improved self-boost efficiency and preventing false writes by ensuring the channel can be effectively cut off during writing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional self-boost type memory cells are used, then the memory device can operate with simple structure, but the channel potential cannot be raised sufficiently leading to decreased boost efficiency
Solution Approach 1:
The gate structure is segmented into multiple independent gates (first gate, second gate, third gate) that can be controlled separately. This segmentation allows different gates to perform different functions: the first gate controls the selected memory cell, while the second and third gates raise the channel potential of non-selected memory cells to cut off their channels and prevent false writes, thereby improving boost efficiency without requiring complete structural redesign
Solution Approach 2:
The second gate and third gate act as intermediary elements that mediate the channel potential control between the selected and non-selected memory cells. By applying specific voltages to these intermediary gates, the channel potential of non-selected cells is raised to cut off their channels, preventing hot electron injection and false writes while maintaining the overall memory cell structure
2Reliability
If the channel is not cut off from selected memory cell to source side memory cells, then the memory device operates with simpler control, but electrons are generated by GIDL and accumulated in floating gate causing false writes
Solution Approach 1:
Before the write operation to the selected memory cell, voltages are preliminarily applied to the second gate and third gate to raise the channel potential of non-selected memory cells on the source side. This preliminary action cuts off the channels of these cells in advance, preventing GIDL-generated electrons from being injected into their floating gates, thereby ensuring data write accuracy
Solution Approach 2:
The voltage parameters of the second gate and third gate are changed during different operation phases. During write operations, specific voltages are applied to these gates to cut off non-selected cell channels. During read operations, different voltage levels are used to ensure proper cell selection. This dynamic parameter adjustment enables precise control over channel cutoff without requiring additional control lines
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances data write reliability by preventing false data writes and improving boost efficiency, ensuring accurate data retention and storage in NAND-type flash memory devices.
Implementation Method 1
memory cell transistors each of which has a stacked gate including a charge accumulation layer and a control gate, and is configured to retain at least two levels of '0' data and '1' data according to a threshold voltage
Data Source
AI summary
A semiconductor memory device includes memory cell transistors, a first selection transistor, and word lines. Each of the memory cell transistors has a stacked gate including a charge accumulation layer and a control gate, and is configured to retain at least two levels of “0” data and “1” data according to a threshold voltage. The threshold voltage corresponding to the “0” data being the lowest threshold voltage in the levels retained by each of the memory cell transistors. The first selection transistor has a current path connected in series to one of the memory cell transistors. Each of the word lines is connected to the control gate of one of the memory cell transistors. upper limit values of threshold voltages of the memory cell transistors retaining the “0” data being different from one another in each word line.