Source Follower Sense Amplifier for Low-Voltage NAND Flash Read Accuracy
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Solution Overview
Problem
Current semiconductor memory systems face challenges in reading data from all bit lines simultaneously while maintaining low read determination thresholds, especially when external voltage sources are low, and are prone to erroneous readings due to variations in current and voltage distributions across memory cells.
Innovation Solution
The implementation of a semiconductor memory apparatus using a source follower sense (SFS) method, which includes a sense amplifier configured to detect current flowing through bit lines and manage voltage levels to accurately read data from all bit lines simultaneously, with a constant current source and specific voltage settings to prevent backflow and erroneous readings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a negative threshold of a memory cell is read by raising the source voltage to virtually apply a negative potential, then the read determination threshold can be lowered, but power consumption increases and current distribution variations cause erroneous readings
Solution Approach 1:
A source follower circuit is introduced as an intermediary between the memory cell and the bit line. This circuit allows the source voltage to be raised to apply a negative potential for reading negative thresholds while preventing direct connection that would cause current backflow. The source follower acts as a buffer that isolates the bit line from voltage fluctuations at the source, enabling low threshold reading without excessive power consumption or current distribution variations
2Productivity
If all bit lines are read simultaneously, then productivity is improved, but voltage and current variations across memory cells cause measurement errors
Solution Approach 1:
The source follower circuit maintains a stable voltage relationship between the source and the bit line by keeping the gate-source voltage constant. This equipotential relationship ensures that even when reading all bit lines simultaneously, voltage variations across different memory cells do not cause measurement errors, as each bit line reading occurs under equivalent voltage conditions
Data Source
AI summary
According to one embodiment, a semiconductor memory apparatus includes an array, a source, a bit line, a sense, and current circuit. The array includes a NAND string. The NAND string includes memory cell. The sense includes a first transistor. One end of transistor is connected to a first node, and other end of the transistor is connected to a second. The first node is used for reading the data held by the memory cell. An internal voltage is smaller than the source voltage. The current circuit outputs a first voltage to a gate of the transistor, and the first voltage is smaller than the internal voltage. The transistor limits a first current from the source to the sense based on a threshold voltage of the memory cell to be read.