Semiconductor Memory Device Erase Sequence Control
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Solution Overview
Problem
Current semiconductor memory devices face inefficiencies in data erasing, leading to loss of valid memory cells due to current leaks, which reduces the utilization of memory cells and affects the reliability of erase operations.
Innovation Solution
A semiconductor memory device with a detection circuit that identifies current leaks during the erase operation, allowing for selective execution of the erase sequence only on valid blocks, thereby preventing unnecessary voltage drops and maintaining the integrity of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase operation is executed on all blocks, then data erasure is performed, but current leaks cause loss of valid memory cells
Solution Approach 1:
The patent applies preliminary action by performing a detection operation before the erase operation to identify blocks with current leaks. The detection circuit checks each block for current leak conditions, and only blocks passing the detection proceed to the erase operation. This prevents valid memory cells from being lost due to erasing blocks that should have been excluded based on current leak characteristics.
2Reliability
If detection circuit is added to identify current leaks, then valid blocks are protected, but device complexity increases
Solution Approach 1:
The detection circuit is designed to perform multiple functions: it detects current leaks during the detection operation and also serves as part of the overall erase control mechanism. The same circuit infrastructure is used for both detection and erase verification, reducing the need for entirely separate dedicated circuits and thereby minimizing the increase in device complexity.
3Loss of substance
If erase sequence is stopped for blocks with current leaks, then valid cells are preserved, but productivity decreases
Solution Approach 1:
The patent extracts or separates the blocks with current leaks from the erase operation process. By identifying these problematic blocks through the detection circuit and excluding them from the erase sequence, the system processes only valid blocks. This extraction approach preserves valid memory cells while maintaining efficient erase operations on the remaining usable blocks, rather than attempting to process all blocks uniformly.
Data Source
AI summary
A memory includes a plurality of planes, a controller, and a source line. The controller is configured to erase data of each memory cell in an erase target block selected in each of the planes, by executing an erase sequence that repeats a plurality of loops, each of the loops including a set of an erase operation that erases the data of each memory cell in the erase target block and an erase verification operation that checks whether the data is erased. For each erase target block, the controller is configured to detect whether there is a current leak from the source line, determine validity of the erase sequence based on a detection result, and stop execution of the erase sequence for the erase target blocks that are determined not to be valid.