3D NAND Split Ground Selection Line Architecture
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Solution Overview
Problem
The existing 3D nonvolatile memory devices with a split ground selection line structure face challenges in reducing the loading on word lines, which affects the operation performance and integration density, particularly in vertical NAND flash memory devices.
Innovation Solution
The implementation of a nonvolatile memory device with multiple memory blocks, each having individually electrically separated ground selection lines, and a row decoder that uses a pass transistor to transfer ground selection signals to multiple memory blocks, reducing the chip area occupied by the row decoder and minimizing word line loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a split ground selection line structure is used in 3D nonvolatile memory devices, then word line loading is reduced, but the device complexity increases due to multiple electrically separated ground selection lines
Solution Approach 1:
The ground selection line is divided into multiple electrically separated segments (first ground selection line and second ground selection line) that can be independently controlled. This segmentation allows different voltage levels to be applied to different portions of the memory block, reducing the capacitive loading on individual word lines while maintaining selective access to memory cells.
Solution Approach 2:
The patent implements dynamic control of ground selection lines through pass transistors that can selectively connect or disconnect different ground selection line segments based on the desired memory block. This dynamic switching capability enables flexible voltage distribution and reduces word line loading only when needed, rather than requiring all ground selection lines to be permanently separated.
2Productivity
If multiple electrically separated ground selection lines are implemented, then operation performance is improved, but the chip area occupied by the row decoder increases
Solution Approach 1:
The pass transistors in the row decoder are designed to perform multiple functions: they serve as both selection switches for different memory blocks and as voltage level translators for the ground selection lines. This multi-functionality reduces the need for dedicated control circuitry, thereby minimizing the additional chip area required despite the increased complexity of multiple ground selection lines.
3Quantity of substance
If ground selection lines are electrically separated for multiple memory blocks, then integration density is improved, but the device complexity increases
Solution Approach 1:
The patent extends the ground selection line structure into the vertical dimension by stacking multiple memory blocks with their respective ground selection lines in three-dimensional space. This vertical stacking allows increased integration density without proportionally increasing the horizontal chip area, while the pass transistor-based control mechanism manages the complexity of interconnecting these vertically stacked blocks.
Data Source
AI summary
A nonvolatile memory device includes a plurality of vertical NAND flash memory cells arranged in a three dimensional (3D) structure, a first memory block disposed in the 3D structure and having memory cells selected by a first ground selection line and a second ground selection line, wherein the first and second ground selection lines are electrically separated from each other, a second memory block disposed in the 3D structure and having memory cells selected by a third selection line and fourth selection line, wherein the third and fourth ground selection lines are electrically separated from each other, and a pass transistor that transfers a driving signal to turn on ground selection transistors respectively connected to the first and third ground selection lines in response to a block selection signal.