Semiconductor Storage Erase Verification via Line Resistance Measurement
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Solution Overview
Problem
In semiconductor storage devices, high resistance in control signal lines due to defects can lead to uncorrectable errors during data reading, as the existing verification methods may incorrectly pass the erase and program verify operations despite contact defects, causing potential data corruption.
Innovation Solution
A semiconductor storage device with a resistance measurement circuit that determines the status of erase verification by measuring the resistance of control signal lines, such as word lines, to accurately assess the integrity of the erase operation and prevent uncorrectable read errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing verification methods are used for erase and program operations, then the verification process is simple and fast, but high resistance in control signal lines can cause uncorrectable read errors to be missed
Solution Approach 1:
The resistance measurement is performed as a preliminary action before the data read operation. By measuring the resistance of control signal lines (word lines, bit lines, select lines) before reading data, the system proactively identifies potential high resistance defects that could cause read errors, preventing them from affecting data integrity without requiring complex real-time monitoring during read operations
Solution Approach 2:
A resistance measurement circuit is introduced as an intermediary component between the control signal lines and the data read path. This intermediary measures the resistance of control signal lines and provides feedback to the control circuit, which then determines whether to proceed with the read operation or report an error, thereby mediating between the simple read operation and the need for reliable error detection
2Reliability
If resistance measurement is performed on control signal lines, then high resistance defects can be detected, but the verification time and process complexity increase
Solution Approach 1:
The resistance measurement is performed as a preliminary action before the data read operation. By measuring the resistance of control signal lines (word lines, bit lines, select lines) before reading data, the system proactively identifies potential high resistance defects that could cause read errors, preventing them from affecting data integrity without requiring complex real-time monitoring during read operations
Solution Approach 2:
The resistance measurement circuit uses the existing control signal lines and verification operations to perform self-diagnosis. The circuit measures resistance using the same infrastructure (control signal lines, memory cells) already present in the device, without requiring separate dedicated measurement hardware or complex external testing equipment, thereby minimizing the time and resource overhead
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents uncorrectable read errors by detecting high resistance in control signal lines and adjusting the status of erase verification, ensuring data integrity and accuracy in semiconductor storage devices.
Implementation Method 1
a resistance measurement circuit configured to measure resistance of a control signal line
Data Source
AI summary
A semiconductor storage device of an embodiment includes a memory block, a resistance measurement circuit, and a control circuit. The memory block includes first to third control signal lines connected to gates of a first select gate transistor, a plurality of memory cell transistors, and a second select gate transistor. The resistance measurement circuit measures resistance of at least one control signal line among the first to third control signal lines. The control circuit performs erase, program, and read of data at the plurality of memory cell transistors included in the memory block. The control circuit determines, based on a measurement result of the resistance measurement by the resistance measurement circuit, whether to set a fail status to a result of erase verify that verifies the erase.