Sectional Data Lines in 3D Memory Arrays
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Solution Overview
Problem
Three-dimensional memory arrays face electrical disadvantages due to high capacitance and resistance in bit line paths, leading to increased power dissipation and voltage drops, which affect sensing speed and chip area efficiency.
Innovation Solution
A sectional data line scheme is implemented, where local data lines are placed in lower metal layers with higher resistance and capacitance, and global data lines are in top metal layers with lower resistance and capacitance, reducing overall resistance and capacitance by using selection circuits to connect bit lines to local and global data lines efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a large fan-out is used to reduce vertical connections and chip area, then chip area efficiency is improved, but capacitance and resistance of array lines increase
Solution Approach 1:
The bit line path is segmented into multiple sections with individual sense amplifiers placed between sections. This segmentation reduces the effective length of data lines that need to be driven, thereby reducing capacitance and resistance effects while maintaining large fan-out for chip area efficiency.
Solution Approach 2:
Individual sense amplifiers are introduced as intermediary components between bit line sections. These sense amplifiers act as mediators that actively drive the data lines, compensating for the increased capacitance and resistance effects in high fan-out configurations.
2Area of stationary object
If a large fan-out is used to reduce vertical connections, then chip area efficiency is improved, but sensing speed is reduced due to increased capacitance
Solution Approach 1:
The bit line path is divided into segments with sense amplifiers positioned between them. This segmentation reduces the capacitance load on each individual sense amplifier, enabling faster sensing speeds while maintaining large fan-out for compact chip area.
Solution Approach 2:
Sense amplifiers serve as intermediary devices that actively compensate for capacitance effects. By placing these amplifiers at strategic intervals along the bit line path, sensing speed is maintained even in high fan-out configurations that minimize chip area.
3Power
If resistance on bit line path is reduced to improve voltage, then voltage drop is reduced, but capacitance on bit line path increases affecting sensing speed
Solution Approach 1:
The bit line path is segmented into multiple sections with sense amplifiers between sections. This reduces the effective resistance by providing multiple parallel conduction paths while the localized capacitance effect is minimized by the shorter segment lengths.
Solution Approach 2:
Sense amplifiers act as intermediary components that provide active driving capability. These amplifiers compensate for resistance effects and maintain voltage levels while their localized placement minimizes the impact of capacitance on sensing speed.
Data Source
AI summary
The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.