PRD Memory Bit Slices for Low-Current Programming
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Solution Overview
Problem
Conventional Programmable Resistive Device (PRD) memory designs are complex and inefficient for generating low-bit-count PRD in standard cell libraries, requiring high voltage and custom designs, which are costly and sensitive to process variations, making them unsuitable for effective low-bit-count PRD generation.
Innovation Solution
A low-bit-count PRD memory is designed using standard cell libraries with bit slices organized as shift registers, incorporating a PRD element, program selector, and latch as a sense amplifier, allowing for programming by voltage application, and optimized for standard cell library design formats, reducing program current and voltage to near supply voltage levels, enabling area-efficient and cost-effective production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional OTP memory design with shared pin and program pad is used, then programming capability is achieved, but program current is very high (60 mA) causing damage to other fuses and interlayer dielectric
Solution Approach 1:
The patent divides the memory into multiple independent bit slices, each with its own program selector and control logic. This segmentation allows individual cells to be programmed with much lower current (microampere range) compared to conventional shared-pad designs that require 60 mA, preventing damage to surrounding structures.
Solution Approach 2:
The patent introduces a program selector (transistor) as an intermediary between the program pad and the fuse. This selector acts as a gate that controls current flow to specific cells, enabling precise cell selection and dramatically reducing the current required for programming compared to direct connection methods.
2Reliability
If conventional OTP cell design is used, then programming function is achieved, but area per cell is very large (150 um2)
Solution Approach 1:
The patent merges multiple functions into the bit slice structure: the program selector, sense amplifier, and fuse control are integrated into a compact unit. This consolidation reduces the area per cell from 150 um2 to a much smaller footprint by eliminating redundant structures and sharing common elements across multiple cells.
Solution Approach 2:
The bit slice design creates a universal cell structure that can perform multiple functions: data storage, sensing, and selective programming. This multi-functional approach eliminates the need for separate dedicated structures for each function, thereby reducing overall cell area while maintaining full programming capability.
3Reliability
If conventional PRD memory design is used, then memory functionality is achieved, but design complexity is high and requires custom design flows
Solution Approach 1:
The patent segments the memory into standardized bit slices that can be independently designed and then replicated. This modular approach simplifies the overall design process by breaking down complex memory structures into manageable, reusable units that follow standard cell library formats.
Solution Approach 2:
The patent changes the design parameters to match standard cell library specifications, including cell height, width, and port locations. This parameter standardization allows the memory to be implemented using conventional EDA tools and standard design flows, eliminating the need for custom design processes while maintaining full memory functionality.
4Reliability
If conventional PRD memory is used, then programming capability is achieved, but sensitivity to process variations is high
Solution Approach 1:
The patent incorporates sense amplifiers that provide feedback mechanisms to detect and compensate for process variations. These amplifiers monitor the state of fuses and adjust sensing thresholds dynamically, reducing sensitivity to manufacturing variations and ensuring reliable read operations across different process conditions.
Solution Approach 2:
The design includes margin built into the sensing and programming circuits to accommodate expected process variations. By designing with sufficient noise margins and voltage headroom beforehand, the memory maintains reliable operation across process corners without requiring complex adaptive compensation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for efficient generation of low-bit-count PRD memory with reduced program current and voltage, simplifying design flows, and optimizing performance by fitting into standard logic design rules, making it cost-effective and area-efficient while being less sensitive to process variations.
Implementation Method 1
programming a fuse, a high voltage can be applied between the pad 8 and pad 7 to conduct a high current flowing through the OTP element 5 to break the fuse into a high resistance state
Implementation Method 2
The OTP element is usually an electrical fuse that is fabricated from polysilicon, silicided polysilicon, or metal in CMOS processes
Implementation Method 3
The program selector 12 can be turned on by asserting a control terminal Sel. The program selector 12 is usually constructed from a MOS device
Implementation Method 4
The program selector 17 can be constructed from a diode that can be embodied as a junction diode with at least one P+ active region on an N well, or a diode with P+ and N+ implants on two ends of a polysilicon substrate
Data Source
AI summary
Architecture, design, structure, layout, and method of forming a Programmable Resistive Device (PRD) memory in standard cell library are disclosed. The PRD memory has a plurality of PRD cells. At least one of the PRD cells can have a PRD element coupled to a first supply voltage line and coupled to a second supply voltage line through a program selector. The PRD cells reside in a standard cell library and following most of the standard cell design and layout guidelines.