Hetero-Plane Flash Memory With Segmented Word Line Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory devices face challenges in increasing storage capacity while maintaining performance, as adding more word line layers can decrease performance and smaller planes are not cost-scalable, and combining different types of planes introduces layout issues with peripheral circuitry control.
Innovation Solution
A hetero-plane data storage structure is implemented, combining different types of planes with optimized peripheral circuitry, where high-performance planes are integrated with cost-scalable planes, with the peripheral circuitry arranged in a CMOS under array (CUA) architecture underneath the memory cells, and bonding pads for interface connections, allowing for efficient storage and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional word line layers are added to increase storage capacity, then storage capacity is improved, but performance deteriorates
Solution Approach 1:
The memory array is divided into multiple planes, each with different numbers of word line layers. This segmentation allows some planes to have more word lines for capacity while others have fewer for performance, resolving the contradiction between storage capacity and performance.
Solution Approach 2:
Different planes within the same memory device are given different local qualities - specifically, different numbers of word line layers and different bit line lengths tailored to their specific performance or capacity requirements, allowing optimization of both capacity and performance simultaneously.
2Speed
If smaller planes are used to minimize read latency, then performance is improved, but cost scalability deteriorates
Solution Approach 1:
The memory device is segmented into different plane types - high-performance planes with fewer word lines for low latency and cost-scalable planes with more word lines for capacity. This allows the system to achieve both low latency and cost scalability by using appropriate plane types in appropriate locations.
Solution Approach 2:
Multiple plane types are merged into a single memory die, combining the advantages of both high-performance and cost-scalable planes. The peripheral circuitry is designed to support both plane types, achieving both low latency and cost scalability in one device.
3Adaptability or versatility
If different types of planes are combined to optimize scalability and performance, then both scalability and performance are improved, but layout complexity increases
Solution Approach 1:
The peripheral circuitry is designed with multi-functionality to support different plane types. The same peripheral circuitry can service both high-performance planes and cost-scalable planes, reducing the need for separate dedicated circuits for each plane type and thereby reducing overall layout complexity.
Solution Approach 2:
Different plane types and their associated peripheral circuitry are merged into a unified layout. By integrating multiple plane types and sharing peripheral resources, the overall layout complexity is managed more effectively than if separate dedicated layouts were used for each plane type.
Data Source
AI summary
A flash memory die includes (i) a first subset of planes including blocks of flash memory cells connected to a first number of word line layers and a plurality of bit lines having a first length, (ii) a second subset of planes including blocks of flash memory cells connected to a second number of word line layers less than the first number of word line layers and a plurality of bit lines having a second length shorter than the first length, (iii) first peripheral circuitry implemented underneath the first subset of planes and including first sense amplifier circuitry and first peripheral control circuitry connected to the first subset of planes, and second peripheral control circuitry connected to the second subset of planes, and (iv) second peripheral circuitry implemented underneath the second subset of planes and including second sense amplifier circuitry connected to the second subset of planes.