Sequential Latch Array Area and Power Reduction
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Solution Overview
Problem
Conventional logic synthesis systems generate latch arrays that are limited by the use of master flip-flops and N-to-1 multiplexors, leading to excessive space occupation, timing limitations, and power consumption, which negatively impact design characteristics such as testability, area, and timing.
Innovation Solution
The generation of synchronous sequential latch arrays using N/2 rows of master-slave latch pairs instead of flip-flops, accompanied by an N/2-to-1 multiplexer and control logic, which eliminates the need for a test harness and reduces power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If master flip-flops and N-to-1 multiplexors are used in latch array design, then the design can be implemented with conventional logic synthesis systems, but the layout area occupied increases and timing performance deteriorates
Solution Approach 1:
The patent extracts and removes the master flip-flop from the conventional latch array structure, replacing it with a simplified latch configuration. This extraction eliminates the need for the flip-flop component while maintaining the essential storage functionality, thereby reducing the layout area occupied by the latch array.
Solution Approach 2:
The patent merges the functionality of the master flip-flop and slave latch into a unified latch structure. By combining these separate components into a single integrated unit, the design reduces the total component count and layout area while preserving the sequential access functionality.
2Ease of manufacture
If master flip-flops and N-to-1 multiplexors are used in latch array design, then the design can be implemented with conventional logic synthesis systems, but timing limitations occur
Solution Approach 1:
The patent extracts the master flip-flop component from the conventional design, removing the timing delays associated with flip-flop operation. This extraction allows the latch array to operate with reduced timing constraints and improved signal propagation speed.
Solution Approach 2:
The patent inverts the conventional approach by eliminating the clocked flip-flop mechanism and using an alternative latch configuration that achieves sequential access without the timing overhead of traditional flip-flop-based designs.
3Ease of manufacture
If master flip-flops and N-to-1 multiplexors are used in latch array design, then the design can be implemented, but power consumption increases
Solution Approach 1:
The patent extracts and removes the master flip-flop from the design, eliminating the power consumption associated with flip-flop operation. This reduction in active components directly decreases the overall power consumption of the latch array while maintaining functionality.
Solution Approach 2:
The patent discards the power-intensive master flip-flop component and recovers the essential storage functionality through a simpler latch structure that consumes less power, achieving both functional equivalence and energy efficiency.
4Reliability
If a test harness is required for scan-testing, then complete test coverage can be achieved, but layout area increases
Solution Approach 1:
The patent implements self-service testability by designing the latch array with intrinsic scan-test capabilities that do not require an external test harness. The latch structure itself provides the necessary test access points and control mechanisms, allowing complete test coverage without additional area-consuming test infrastructure.
Data Source
AI summary
A synchronous sequential latch array generated by an automated system for generating master-slave latch structures is disclosed. A master-slave latch structure includes N/2 rows of master-slave latch pairs, an N/2-to-1 multiplexer and control logic. N is equal to the number of latches that are included in the latch array.