Nonvolatile Memory Refresh via Threshold Voltage Verification
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Solution Overview
Problem
Nonvolatile memory systems, particularly NAND flash memory, face challenges in maintaining accurate data retrieval due to shifts in threshold voltage distributions over time, leading to data retention errors and program disturb issues, which affect the reliability of read operations and data integrity.
Innovation Solution
A memory system that includes a control circuit capable of executing a reprogramming refresh process, where memory cells are verified using specific voltage corrections to maintain optimal threshold voltage distributions, and a flag table is used to determine when to apply reprogramming or block refresh processes to mitigate data retention errors and program disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory cells are read repeatedly over time, then data retrieval speed is maintained, but threshold voltage distributions shift causing data retention errors
Solution Approach 1:
The patent performs preliminary verification of threshold voltage distributions before data becomes unreliable. The control circuit monitors threshold voltage shifts and proactively initiates refresh operations before data retention errors occur, preventing the contradiction from manifesting by acting in advance when threshold voltage drift is detected but before it causes reading failures
Solution Approach 2:
The patent implements a feedback mechanism where the control circuit continuously monitors threshold voltage distributions of memory cells and adjusts refresh operations accordingly. When threshold voltage shifts are detected through verification operations, the system feeds this information back to trigger targeted refresh operations on affected memory blocks, dynamically balancing read speed and data retention reliability
2Reliability
If refresh operations are performed frequently, then data retention errors are reduced, but system productivity decreases
Solution Approach 1:
The patent applies local quality by performing refresh operations selectively on only those memory blocks that exhibit threshold voltage shifts, rather than refreshing the entire memory array. The control circuit identifies specific blocks needing refresh based on verification results and applies refresh operations locally to those blocks only, maintaining high productivity while ensuring data retention reliability where needed
Solution Approach 2:
The patent uses partial action by performing verification and refresh operations on a subset of memory cells rather than all cells. The system verifies threshold voltages of selected memory cells and performs refresh operations only on those showing drift, avoiding excessive full-array refresh operations that would reduce productivity, while still maintaining adequate data retention reliability
3Measurement precision
If verification voltage margins are increased, then reading accuracy is improved, but program disturb issues increase
Solution Approach 1:
The patent implements dynamic verification voltage selection where the control circuit adjusts verification voltages based on actual threshold voltage distributions measured in the memory cells. Rather than using fixed conservative margins that cause program disturb, the system dynamically sets verification voltages close to actual threshold values when drift is detected, improving reading accuracy without excessive safety margins that would cause harmful program disturb effects
Solution Approach 2:
The patent changes the verification voltage parameter dynamically based on detected threshold voltage shifts. When threshold voltage drift is detected, the control circuit adjusts verification voltages to match the new distribution, optimizing reading accuracy for the current state. This parameter adaptation prevents the need for consistently high verification margins that would cause program disturb, achieving accurate readings only when necessary
Data Source
AI summary
According to one embodiment, a nonvolatile memory includes: a memory cell array including memory cells; and a controller configured to execute a first refresh process on receiving a first command. The first refresh process includes reprogramming at least one second memory cell among first memory cells to which data has been programmed in a first group. In executing the first refresh process, the controller is configured to: select the second memory cell by verifying with a first voltage using a first amount in a case where the second memory cell has been programmed using the first voltage; and select the second memory cell by verifying with a second voltage using a second amount in a case where the second memory cell has been programmed using the second voltage.