Memory Device Precharge Mechanism for Readout Speed
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Solution Overview
Problem
Conventional memory devices, particularly RAMs like DRAMs, experience significant delays during memory cell readout due to the time required for bit line charging, evaluation, and gate delay, which affects overall performance.
Innovation Solution
The introduction of a memory device with an evaluation circuit and a precharge mechanism that sets the output voltage to 0.5*Usupply before bit line precharging, reducing the evaluation time and gate delay by precharging the output of the current mirror devices to a predetermined voltage level, thereby accelerating the readout process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bit line precharging is performed before memory cell readout, then the bit line is charged to a predetermined voltage level, but this process consumes significant time (t1) and delays the overall readout speed
Solution Approach 1:
The patent applies preliminary action by precharging the output of the current mirror devices to 0.5*Usupply voltage before the actual memory cell readout operation begins. This preliminary precharging of the evaluation circuit output, combined with simultaneous bit line precharging, allows the system to be ready for immediate evaluation when the readout starts, thereby reducing the overall readout time while maintaining voltage stability
2Measurement precision
If the output of current mirror devices is connected to inverters for signal evaluation, then the read current can be compared with reference current, but this introduces additional gate delay time (τgate delay) that slows down the readout process
Solution Approach 1:
The patent changes the voltage parameter of the evaluation circuit output by precharging it to 0.5*Usupply before readout. This parameter change allows the output to reach the required evaluation voltage levels faster, reducing the evaluation time (t2) and gate delay while maintaining the accuracy of current comparison through the inverter circuit
3Productivity
If the evaluation circuit output is precharged to 0.5*Usupply before bit line precharging, then the overall readout time is reduced, but this requires an additional precharge mechanism and control logic
Solution Approach 1:
The patent merges the precharging operations by using a single control signal to simultaneously control both the bit line precharge circuit and the evaluation circuit output precharge mechanism. This unified approach achieves the dual precharging function without proportionally increasing device complexity, as the control logic is integrated rather than duplicated
Data Source
AI summary
A memory device, including a non-volatile memory device, a method for operating a memory device, and an apparatus for use with a memory device is disclosed. In one embodiment, the memory device includes at least one evaluation circuit for amplifying a signal resulting from the reading of a memory cell, and a device for precharging an output of the evaluation circuit to a predetermined voltage level.