NAND Flash Memory Reading Negative Threshold Voltage
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Solution Overview
Problem
In NAND flash memory, the large maximum voltage difference between negative and positive threshold voltage distributions leads to capacitive interference, making accurate reading challenging, and existing solutions require a negative-voltage-generating circuit or triple-well structure, which hinders miniaturization and integration.
Innovation Solution
A reading method that pre-charges a selected bit line, applies a voltage to a non-selected word line to turn on memory cells regardless of their status, and uses a positive voltage applied to the source line and adjacent bit line to read negative threshold voltages without a negative-voltage-generating circuit or triple-well structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a negative-voltage-generating circuit or triple-well structure is used to read negative threshold voltages, then accurate reading of memory cells is achieved, but device area increases and integration is hindered
Solution Approach 1:
The patent extracts the negative voltage generation function from a separate dedicated circuit and integrates it into the existing word line structure. By applying positive voltage to the P-well, the invention generates the necessary negative threshold voltage reading capability directly at the memory cell location, eliminating the need for a separate negative-voltage-generating circuit and reducing device area.
Solution Approach 2:
The word line structure is given multiple functions: it serves both as a standard control line for memory operations and as a source for generating negative threshold voltage potentials during reading operations. The P-well structure similarly serves dual purposes as both a device fabrication element and a voltage generation mechanism, eliminating dedicated negative voltage generation hardware.
2Object-affected harmful factors
If the maximum voltage difference between negative and positive threshold voltage distributions is reduced, then capacitive interference is minimized, but control over threshold voltage distribution becomes more difficult
Solution Approach 1:
The P-well acts as an intermediary element that mediates between the applied positive voltage and the memory cell threshold voltage. By controlling the P-well potential, the invention indirectly controls the effective voltage difference across the memory cell, reducing capacitive interference while maintaining manageable voltage control through the P-well connection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables accurate reading of negative threshold voltages without the need for a negative-voltage-generating circuit or triple-well structure, allowing for miniaturization and high integration of NAND flash memory devices.
Implementation Method 1
a positive voltage is applied to a source line, a P-well formed with a selected memory cell and an adjacent non-selected bit line
Data Source
AI summary
The disclosure provides a NAND flash memory and a reading method thereof, which may read a negative threshold value of a memory cell without using a negative-voltage-generating circuit. The disclosed NAND flash memory includes a sense amplifier, a bit line selecting circuit and an array having a plurality of NAND string units. The disclosed NAND flash memory includes a ΔV supplying portion element that applies a positive voltage to a source line, a P well formed with a selected memory cell, and a non-selected bit line which is adjacent to a selected bit line, within a predetermined time period, after the selected bit line is pre-charged and during a reading process.