Nonvolatile Memory Write Circuit Voltage Control

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Solution Overview

Problem

Conventional 2Tr flash memory devices face issues with faulty write operations due to large voltage differences between the drain electrodes and substrate of non-selected memory cells, leading to weak write states, as the negative voltage applied to the substrate affects all memory cells during write operations.

Innovation Solution

A nonvolatile semiconductor memory device with a write circuit that controls voltages to lower the negative side power supply voltage to an intermediate value before reducing the positive side power supply voltage, minimizing the voltage difference and preventing data destruction, while maintaining the intermediate value for a certain time to ensure accurate data writing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the negative voltage is applied to the substrate part of all memory cells during write operation, then the write operation can be executed, but a large voltage difference is applied between drain electrodes and substrate of non-selected memory cells causing weak write state and faulty write operation

Engineering Contradiction:
Improvewrite operation reliabilityVSAvoidlarge voltage difference effect
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies different voltage levels to different regions: the selected memory cell substrate receives a first negative voltage (e.g., -5V to -10V) while non-selected memory cell substrates receive a second negative voltage (e.g., -2V to -3V). This local differentiation ensures strong write state in selected cells while preventing harmful large voltage differences in non-selected cells.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The substrate voltage control is segmented into multiple levels based on selection status. The write state machine divides the substrate into selected and non-selected regions, applying appropriate voltage levels to each segment. This segmentation allows independent voltage control for different memory cell groups during write operations.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If the voltage applied to the negative side power supply terminal is lowered first, then the voltage control sequence can be executed, but the voltage difference between positive and negative power supply terminals becomes large causing data destruction in latch circuits

Engineering Contradiction:
Improvevoltage control sequenceVSAvoiddata integrity in latch circuits
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The write state machine performs preliminary voltage adjustment by first setting the negative power supply voltage to an intermediate level before adjusting the positive power supply voltage. This preliminary action prevents excessive voltage difference from occurring, thereby protecting latch circuit data while maintaining operational sequence.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent dynamically changes voltage parameters in a controlled sequence: first adjusting the negative power supply voltage to an intermediate value, then adjusting the positive power supply voltage. This parameter change strategy ensures that the voltage difference never exceeds safe thresholds during the transition process.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7876619B2Nonvolatile semiconductor memory device
Publication Date: 2011.01.25 KK TOSHIBA
  • US7876619B2 patent drawing
  • US7876619B2 patent drawing
  • US7876619B2 patent drawing

AI summary

A semiconductor memory device comprises: a write circuit including a latch circuit configured by two inverters having a positive side power supply terminal supplied with a first voltage and a negative side power supply terminal supplied with a second voltage; and a write state machine controlling the first and second voltages. When writing data to a memory cell, the first voltage is changed to a second value that is lower than a first value. When writing data to a memory cell, the second voltage is changed to a third value that is lower than the second value. The write state machine lowers the second voltage to an intermediate value between the second value and the third value and, while maintaining this intermediate value, lowers the first voltage from the first value to the second value.