Memory Retention Margin Verification for Over-Programming Detection
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Solution Overview
Problem
Current memory systems face challenges in detecting over-programming and erroneous errors in memory cells, which can lead to incorrect data storage and require extensive processing time for error correction, especially when programming multiple cells simultaneously.
Innovation Solution
The implementation of a data retention margin bit count verification method, where an extra read is performed in retention margins after the normal program verify sequence to detect failure bits, and a latch accumulates these bits to generate a failure error if they exceed a predetermined threshold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory cells are programmed in parallel to improve productivity, then programming speed increases, but variations in programming speed among different cells occur due to minor structural and operational variations, leading to over-programming and errors
Solution Approach 1:
The patent segments the verification process into multiple stages: initial program verify to check minimum threshold voltage, followed by retention margin verification to check upper threshold limits. This segmentation allows different verification objectives to be achieved separately, improving both productivity and reliability by not slowing down the overall process while adding comprehensive checking.
Solution Approach 2:
The patent performs preliminary verification during the programming process itself by incorporating retention margin checks between programming pulses. This preliminary detection of over-programming conditions allows the system to identify and correct issues before they manifest as errors, maintaining high programming speed while ensuring accuracy.
2Reliability
If traditional verify operations are performed to detect programming errors, then error detection capability improves, but processing time increases significantly due to extensive error correction requirements
Solution Approach 1:
The patent performs verification actions during the programming process itself rather than only after completion. By checking retention margins between programming pulses and during subsequent read operations, the system detects over-programming conditions early, reducing the need for extensive post-programming error correction and significantly reducing processing time.
Solution Approach 2:
The patent implements feedback mechanisms where the results of retention margin verification are used to determine whether additional programming pulses are needed or if the cell should be skipped. This feedback loop allows the system to adapt dynamically, avoiding unnecessary error correction operations and reducing overall processing time while maintaining high reliability.
Data Source
AI summary
A memory system, comprising an array of storage elements divided into logical blocks and pages within said logical blocks and a managing circuit is provided. The managing circuit is in communication with said array of storage elements and performs programming and reading operations. The programming operations include programming a plurality of multi-state storage data. The reading operations include defining an retention margin between adjacent data thresholds, determining whether bits are present in a portion of the data retention margin, and if the number of bits in the portion of retention margin exceeds a threshold, generating an error.