3D Cross-Point Memory Array for Neural Network Sum-of-Products

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Solution Overview

Problem

Current neuromorphic computing systems face challenges in efficiently implementing high-speed sum-of-products operations due to the need for large arrays and parallel execution of operations, which is not adequately addressed by existing circuitry.

Innovation Solution

A 3D array of cells with programmable conductances is implemented using charge storage structures at cross-points of vertical and horizontal lines, where a gate driver applies control gate voltages and an input driver applies input variables, enabling efficient sum-of-products operations by sensing currents through a sensing circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If large arrays are used to execute many operations in parallel for high-speed sum-of-products operations, then computing speed is improved, but device complexity and data access requirements increase

Engineering Contradiction:
Improvecomputing speedVSAvoidarray size
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent combines memory storage and computing operations into a single integrated structure. The 3D cross-point array serves both as memory for storing weights and as a computing engine for performing sum-of-products operations, eliminating the need for separate memory and processing units and reducing overall system complexity despite large scale.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from traditional 2D memory arrays to a 3D cross-point architecture. By adding the vertical dimension with stacked memory cells at multiple levels (Z-dimension), the system achieves higher density and enables parallel operations across three spatial dimensions, improving computing speed while managing complexity through efficient spatial utilization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If large arrays are implemented for parallel operations, then productivity is improved, but data access between memory device and CPU increases

Engineering Contradiction:
Improveoperation throughputVSAvoiddata access time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The integrated memory-computing architecture enables the system to perform computations directly where data is stored, without requiring data to be transferred to a separate processing unit. The memory device itself executes sum-of-products operations by utilizing the conductance values of its cells, eliminating data access bottlenecks and enabling high throughput operations.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent introduces a sensing circuit as an intermediary component that reads the conductance states of memory cells and converts them into usable computational results. This sensing circuit acts as a bridge between the memory storage medium and the computational output, enabling efficient data retrieval and processing without requiring traditional CPU data access pathways.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If 3D array with charge storage structures is used, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvecell programmabilityVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent utilizes charge storage structures that can be programmed by changing electrical parameters (charge states) rather than requiring physical reconfiguration. The conductance of each cross-point cell can be adjusted continuously by controlling the amount of charge stored, enabling precise weight values for neural network operations without increasing structural complexity.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces traditional mechanical or electrical switching mechanisms with charge-based conductance modulation. Instead of using movable parts or complex switching circuits to set weight values, the system uses electrical charge storage to directly control cell conductance, simplifying the overall device structure while maintaining high programmability precision.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration allows for significant improvements in computing speed by reducing data access between the memory device and central processing unit, enabling efficient execution of sum-of-products operations in large arrays.

Implementation Method 1

the cells having programmable conductances, which can be implemented using charge storage structures disposed at cross-points of the plurality of vertical lines and the plurality of horizontal lines

Methodology Applied
Scientific EffectCharge storage: Capacitance

Implementation Method 2

A sensing circuit senses a sum-of-currents from cells in the 3D array, the sum-of-currents corresponding to the sum-of-products

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS10664746B2Neural network system
Publication Date: 2020.05.26 MACRONIX INTERNATIONAL CO LTD
  • US10664746B2 patent drawing
  • US10664746B2 patent drawing
  • US10664746B2 patent drawing

AI summary

A neural network system for execution of a sum-of-products operation includes a memory device and a controller. The memory device includes a 3D array having a plurality of memory cells with programmable conductances disposed in cross-points of a plurality of cell body lines and gate lines, a gate driver coupled to the gate lines and applying control gate voltages in combination with the programmable conductances for corresponding to weights of terms in the sum-of-products operation, a input driver used to apply voltages to the memory cells corresponding to input variables, a plurality of input lines connecting the cell body lines to the input driver, a sensing circuit used to sense currents passing through the memory cells corresponding the terms in the sum-of-products operation, a buffer circuit used to store the terms. The controller is used to control the memory device summing up the terms in the sum-of-products operation.