Computation Using Non-Contact Making Devices TRIZ Cases
- Multi-Die AI Chip Package for Flexible Neural Network Layer Mapping
Multiple identical AI dies are linked in one chip package so neural network layers can be mapped flexibly while cutting ASIC design time and NRE costs.
- 3D AI Chip Layout With Split Memory and Compute Dies
Separating Fe-RAM memory and matrix compute dies in a 3D AI chip cuts data-transfer latency while raising bandwidth and lowering energy use.
- Multi-Die Matrix Multiplication Using FeRAM for Low-Latency AI
Separating weight storage and compute across memory and compute dies cuts AI matrix multiplication latency and power with high-bandwidth FeRAM access.