Multi-Die AI Chip Package for Flexible Neural Network Layer Mapping

Solution Overview

Problem

The challenges of using custom application-specific integrated circuits (ASICs) for neural network processing include long design times and significant non-recurring engineering costs, which are exacerbated by the increasing popularity and variety of neural network tasks.

Innovation Solution

A standard die configured for neural network tasks is interconnected with multiple identical dies in a single ASIC chip package, where each die corresponds to a layer of the neural network, allowing flexible configuration to process different neural networks efficiently, reducing design time and non-recurring engineering costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If custom ASICs are used for neural network processing, then processing efficiency is improved, but design time and non-recurring engineering costs increase

Engineering Contradiction:

Improveneural network processing efficiencyVSAvoiddesign time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The system segments the neural network processing function into multiple identical processing dies, where each die handles a specific layer or portion of the neural network. This segmentation allows parallel processing while using standardized die designs, thereby improving processing efficiency without requiring custom design for each individual die.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent employs universal processing dies that can be configured to handle different neural network architectures and tasks through software or configuration settings. These identical dies are designed to be multi-functional, allowing the same physical hardware to process various types of neural networks (CNN, RNN, Transformer, etc.) without requiring custom ASIC design for each application.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If custom ASICs are used for neural network processing, then processing efficiency is improved, but non-recurring engineering costs increase

Engineering Contradiction:

Improveneural network processing efficiencyVSAvoidnon-recurring engineering costs

Core Design Contradiction:

ProductivityVSEase of manufacture

Solution Approach 1:

The patent employs universal processing dies that can be configured to handle different neural network architectures and tasks through software or configuration settings. These identical dies are designed to be multi-functional, allowing the same physical hardware to process various types of neural networks (CNN, RNN, Transformer, etc.) without requiring custom ASIC design for each application.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

Instead of designing unique custom ASICs for each neural network application, the patent creates copies of identical processing dies that can be replicated and interconnected in different configurations. This copying approach allows the same standardized die design to be used across multiple applications, significantly reducing non-recurring engineering costs while maintaining high processing efficiency.

Inventive Principle:

Principle #26Copying

3Adaptability or versatility

If multiple identical dies are interconnected, then adaptability to different neural networks is improved, but device complexity increases

Engineering Contradiction:

Improveneural network configuration flexibilityVSAvoidinter-die interconnection complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system segments the neural network processing function into multiple identical processing dies, where each die handles a specific layer or portion of the neural network. This segmentation allows parallel processing while using standardized die designs, thereby improving processing efficiency without requiring custom design for each individual die.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediary components such as standardized inter-die communication interfaces and control logic that mediate between the identical processing dies. These intermediaries provide a uniform method for data transfer and coordination between dies, simplifying the overall system complexity despite having multiple interconnected components.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20250238668A1Apparatus and mechanism for processing neural network tasks using a single chip package with multiple identical dies

Publication Date: 2025.07.24 GOOGLE LLC

AI summary

Apparatus and methods for processing neural network models are provided. The apparatus can comprise a plurality of identical artificial intelligence processing dies. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies can include at least one inter-die input block and at least one inter-die output block. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies is communicatively coupled to another artificial intelligence processing die among the plurality of identical artificial intelligence processing dies by way of one or more communication paths from the at least one inter-die output block of the artificial intelligence processing die to the at least one inter-die input block of the artificial intelligence processing die. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies corresponds to at least one layer of a neural network.