Shared Division and Modulo Logic for Low-Area Multi-Input Arithmetic
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Solution Overview
Problem
Existing systems require multiple dedicated circuits for division and modulo operations, leading to increased chip area and latency, especially in multi-granule memory applications where input numbers are power-of-two multiples or fractions.
Innovation Solution
A device with a single division logic circuit and/or a single modulo logic circuit, utilizing multiplexers and bit-shifting circuits to perform operations on sets of input numbers, allowing for efficient computation of quotients and remainders by using the largest input number as a reference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple dedicated circuits are used for division and modulo operations on each input number, then computation accuracy is maintained, but chip area increases significantly
Solution Approach 1:
A single division logic circuit and a single modulo logic circuit are designed to handle multiple input numbers through sequential processing. The multiplexer routes different input numbers to the same logic circuits at different time slots, allowing one circuit to perform multiple functions that previously required separate dedicated circuits for each input number.
Solution Approach 2:
The system dynamically switches between different input numbers using a multiplexer controlled by a select signal. Instead of having static dedicated circuits for each input, the system uses dynamic routing to connect the appropriate input to the shared logic circuits at the right time, enabling time-multiplexed operation.
2Productivity
If multiple dedicated circuits are used for division and modulo operations, then computation speed is maintained, but latency increases due to more circuits
Solution Approach 1:
The system processes multiple input numbers in periodic cycles, with each input number being processed in sequence through the shared division and modulo logic circuits. The multiplexer switches between inputs in a periodic manner controlled by the select signal, allowing efficient time-multiplexed processing that maintains overall computation speed while reducing the number of physical circuits required.
3Productivity
If dedicated circuits are provided for each input number, then operations can be performed in parallel, but device complexity increases
Solution Approach 1:
Multiple separate division logic circuits and modulo logic circuits are merged into single shared circuits. The multiplexer combines multiple input signals and routes them to the shared logic circuits, effectively combining what were previously separate processing paths into a unified time-multiplexed structure, thereby reducing overall device complexity.
Data Source
AI summary
A device is provided. In some examples, the device includes a division logic circuit having input lines including a first least significant input line. The division logic circuit further includes temporary output lines including a second least significant line. The device also includes a first multiplexer having a first data input coupled to the first least significant input line. The first multiplexer further includes a second data input coupled to the second least significant line.