Floating-Point Conversion Circuit Using Direct Exponent Shifts

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Solution Overview

Problem

Existing binary logic circuits for converting floating point numbers to fixed point numbers face inefficiencies in critical path determination due to the need for exponent bias subtraction and negation of mantissa, particularly in signed negative floating point numbers, which affects conversion speed and complexity.

Innovation Solution

A binary logic circuit utilizing a split-path shifter that left-shifts or right-shifts the mantissa based on the exponent's least significant bits, eliminating the need for exponent bias subtraction and incorporating an inverting unit and multiplexer to handle signed and unsigned formats efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If exponent bias subtraction and mantissa negation are performed in existing conversion circuits, then conversion accuracy is maintained, but conversion speed decreases and circuit complexity increases

Engineering Contradiction:
Improveconversion speedVSAvoidcircuit complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the unnecessary exponent bias subtraction operation from the conversion circuit. By recognizing that the shift amount can be directly obtained from the exponent field without subtracting the bias value, the circuit removes the subtraction unit and its associated critical path delay, thereby improving conversion speed while maintaining accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent inverts the traditional approach by directly using the exponent bits to control the shifter instead of first computing the true exponent through bias subtraction. This inversion of the operational sequence eliminates redundant steps and reduces circuit complexity while achieving the same conversion result.

Inventive Principle:
Principle #13The other way round (Inversion)

2Device complexity

If a single shifter is used for both left and right shifts, then device complexity is reduced, but conversion accuracy may be compromised for different exponent ranges

Engineering Contradiction:
Improvecircuit complexityVSAvoidconversion accuracy
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent implements a dynamic shifter configuration where the shift direction and amount are dynamically determined by the exponent value. The circuit uses conditional logic to select between left-shift and right-shift operations based on the exponent range, allowing a single shifter unit to adaptively handle different conversion scenarios with full accuracy.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent designs a universal shifter unit that can perform both left-shift and right-shift operations depending on the input conditions. By making the shifter multi-functional through conditional control signals derived from the exponent field, the circuit achieves the functionality of multiple specialized shifters while using a single physical unit, thus reducing complexity without sacrificing precision.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12417073B2Floating point to fixed point conversion
Publication Date: 2025.09.16 IMAGINATION TECH LTD
  • US12417073B2 patent drawing
  • US12417073B2 patent drawing
  • US12417073B2 patent drawing

AI summary

A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew−1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew−1), bitwidth(iw−2−sy)}≤k≤(ew−1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.