Multiplier Circuit Using Inversion Compression for Lower Area
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Solution Overview
Problem
Existing multiplier designs based on standard encoders and adders require a large area and high power consumption due to the extensive use of MOS transistors, making them complex and difficult to implement effectively.
Innovation Solution
A multiplier design utilizing P groups of encoders and W layers of inversion compressors, where each group of encoders performs non-inversion or inversion encoding to generate partial products, and the inversion compressors compress these products to obtain the final result, reducing the area and power consumption by simplifying the implementation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard encoders and standard adders are used in multiplier design, then the multiplication function is achieved, but the area occupied by the multiplier becomes large due to the large quantity of MOS transistors
Solution Approach 1:
The patent segments the multiplication process into distinct functional modules: encoding units that generate partial products, compression units that reduce the number of terms, and addition units that compute the final result. This modular segmentation allows each unit to be optimized independently, reducing the total transistor count while maintaining functionality.
Solution Approach 2:
The patent inverts the traditional approach by using non-standard encoder and adder designs that prioritize area efficiency over conventional implementation. Specifically, it uses encoded representations and compression techniques that reduce the number of required MOS transistors compared to standard designs.
2Ease of manufacture
If standard encoders and standard adders are used in multiplier design, then the multiplication function is achieved, but the power consumption increases due to the large quantity of MOS transistors
Solution Approach 1:
By segmenting the computation into encoding, compression, and addition stages, the patent enables power optimization at each stage. The encoding units generate fewer partial products, the compression units reduce term count, and the addition units operate on smaller data, collectively reducing dynamic power consumption.
Solution Approach 2:
The patent changes key parameters of the computational process: using non-radix-2 encodings that produce fewer terms, applying compression ratios that reduce intermediate term counts, and optimizing adder depth. These parameter changes directly reduce the number of switching transistors and their toggle rates, lowering power consumption.
3Ease of manufacture
If standard encoders and standard adders are used in multiplier design, then the multiplication function is achieved, but the device complexity increases due to the large quantity of MOS transistors
Solution Approach 1:
The patent divides the complex multiplication operation into simpler, standardized sub-operations performed by dedicated units. Each unit has a well-defined function with regular structure, making individual units simpler to implement and verify, even though the overall system remains functionally complex.
Solution Approach 2:
The patent designs universal encoding and compression units that can handle different operand sizes and configurations. These multi-functional units reduce the need for multiple specialized circuits, thereby simplifying the overall device architecture while maintaining versatility.
Data Source
AI summary
A multiplier is configured to implement multiplication of a first value of M bits and a second value of N bits, and includes P groups of encoders and W layers of inversion compressors. Each group include N encoders and are configured to encode a part of bits in the second value, and a group selection signal and a symbol control input signal corresponding to the each group. The group selection signal and the symbol control input signal are generated based on a part of bits in the first value, and the P groups of encoders perform encoding to obtain P partial products. The W layers of inversion compressors are configured to compress the P partial products.