Configurable Logic Cell Output Region for Fewer LUT Devices
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Solution Overview
Problem
As the density of lookup table-based circuits increases, maximizing performance while minimizing area and power consumption becomes challenging, leading to a rapid increase in the number of devices needed to implement the circuit.
Innovation Solution
A configurable logic cell with an input selection region, a computation region using multiple four-input lookup tables, and an output region with domino logic stages, allowing for flexible configuration to perform various logic operations and reduce the number of active components during any given operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If lookup table density is increased to improve computation speed, then circuit performance is improved, but the number of devices required increases rapidly
Solution Approach 1:
Multiple lookup tables are merged into a single shared lookup table structure. The patent combines several logic operations that would traditionally require separate lookup tables into one unified lookup table that serves multiple functions, thereby reducing the total number of devices while maintaining computation speed.
Solution Approach 2:
The lookup table is designed to perform multiple logic operations simultaneously or sequentially. A single lookup table structure is configured to handle various logic functions by reconfiguring its internal connections and selection logic, eliminating the need for dedicated lookup tables for each operation.
2Speed
If lookup table density is increased to improve computation speed, then circuit performance is improved, but area consumption increases
Solution Approach 1:
Adjacent lookup tables are merged into a single compact structure. The patent consolidates multiple lookup table functions into one physical structure, reducing the overall area occupied while maintaining the computational capabilities of individual lookup tables through shared resources and multiplexing.
3Speed
If lookup table density is increased to improve computation speed, then circuit performance is improved, but power consumption increases
Solution Approach 1:
Multiple lookup table operations are merged into a single power-efficient structure. By combining several logic operations into one lookup table, the patent reduces the total number of active devices switching simultaneously, thereby lowering overall power consumption while maintaining computation speed through efficient resource sharing.
Data Source
AI summary
Configurable circuits include an input selection region, a computation region, a switching region, and an output region. The input selection region includes a set of input multiplexers and selects and routes input signals. The computation region includes a set of lookup tables, each lookup table being coupled to selected signals from the input selection stage to generate a respective output signal. The switching region includes a set of output multiplexers, each output multiplexer being coupled to output signals from the set of lookup tables to provide circuit outputs responsive to respective output selection signals. The output region includes a domino logic stage, having a set of transistors, coupled to output signals from the set of lookup tables to provide circuit outputs that determine combinations of the signals output by the set of lookup tables.